Method and a deep sub-micron field effect transistor structure for suppressing short channel effects

• US 6,157,064 A
• Filed: 09/07/1999
• Issued: 12/05/2000
• Est. Priority Date: 12/15/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Jenn Ming
• Primary Examiner(s): Loke, Steven H.
• Assistant Examiner(s): Hu, Shouxiang
• Application Number:
  US09/391,885
• Time in Patent Office: 455 Days
• Field of Search: 257/346, 257/336, 257/344, 257/408, 438/305, 438/304, 438/558, 438/559, 438/563, 438/302
• US Class Current: 257/344
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2257 the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method and a deep sub-micron FET structure for suppressing short channel effects and reducing gate-to-drain overlay capacitance and for making CMOS devices is achieved. The method for making these improved FETs includes forming a gate oxide and a patterned polysilicon layer for gate electrodes. Silicon nitride (Si₃ N₄) first sidewall spacers are formed on the sidewalls of the gate electrodes. After selectively removing the gate oxide adjacent to the first sidewall spacers, second sidewall spacers are formed from a doped oxide that serve as a solid-phase diffusion source. The source/drain contact areas are implanted adjacent to the second sidewall spacers. The substrate is then annealed to diffuse from the second sidewall spacers the lightly doped source/drains (LDDs). The Si₃ N₄ sidewall spacers serve as a diffusion barrier and the LDDs are formed finder the Si₃ N₄ spacers contiguous with the FET channel, resulting in reduced gate-to-drain overlay capacitance and improved immunity to hot electron effects. By including three additional masking steps, both N-channel and P-channel FETs can be formed for making CMOS devices.

Claims

1. An improved field effect transistor (FET) with diffused lightly doped source/drain areas comprised of:

a semiconductor substrate doped with a first conductive type dopant and having field oxide areas on said semiconductor substrate surrounding and electrically isolating device areas;

a gate oxide layer on said device areas;

a polysilicon layer doped with a second conductive type dopant on s aid substrate and over said gate oxide and said polysilicon layer patterned to form gate electrodes on said device areas;

first sidewall spacers composed of silicon nitride on sidewalls of said gate electrodes and on said gate oxide;

second sidewall spacers formed from a doped glass as a diffusion layer doped with said second conductive type dopant one said first sidewall spacers and contacting said substrate adjacent to said first sidewall spacers;

doped source/drain areas adjacent to said second sidewall spacers formed by ion implantation of said second conductive type dopant;

lightly doped source/drain areas under said first sidewall spacers and contiguous with the channels of said FETs formed by diffusion of said second conductive type dopant from said second sidewall spacers.

2. The field effect transistor of claim 1, wherein said first conductive type dopant is boron, and said second conductive type dopant is phosphorus, thereby forming N-channel FETs.

3. The field effect transistor of claim 1, wherein said first conductive type dopant is phosphorus, and said second conductive type dopant is boron, thereby forming P-channel FETs.