Delay stabilization system for an integrated circuit

• US 6,157,231 A
• Filed: 03/19/1999
• Issued: 12/05/2000
• Est. Priority Date: 03/19/1999
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: Credence Systems Corporation (COHU Incorporated)
• Inventors: Wasson, Timothy M.
• Primary Examiner(s): Lam, Tuan T.
• Application Number:
  US09/272,803
• Time in Patent Office: 627 Days
• Field of Search: 327/149, 327/150, 327/152, 327/153, 327/458, 327/159, 327/161-163, 327/262, 327/269, 327/270, 327/276, 327/277, 327/244, 327/245, 327/236, 327/535, 327/156
• US Class Current: 327/156
• CPC Class Codes: H03K 2005/00097 Avoiding variations of delay using feedback, e.g. controlled by a PLL
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

Abstract

A system for stabilizing a delay through a signal path of an integrated circuit (IC) includes an oscillator for producing a periodic first reference signal, a delay circuit for delaying the first reference signal to produce a periodic second reference signal, and a loop controller for adjusting the magnitude of the IC'"'"'s power supply so as to maintain a constant phase difference between the first and second reference signals. By adjusting the power supply magnitude, the loop controller also stabilizes signal path delays through logic circuits implemented in the IC. The oscillator is formed by a logic gate implemented in the IC and a passive delay line feeding the logic gate'"'"'s output back to its input. The delay of the delay circuit is programmably adjustable to allow for adjustment of the signal path delay through the IC.

Claims

1. A system for stabilizing a delay through a signal path of an integrated circuit (IC), wherein said signal path is formed by first transistors, wherein said delay depends on signal propagation speed of said first transistors which is in turn influenced by a temperature of said IC and by a magnitude of a power supply signal applied to said IC, the system comprising:

an oscillator for producing a periodic first reference signal, said oscillator comprising gate means internal to said IC having an input and an output and delay means external to said IC for connecting said input to said output,

a delay circuit for delaying said first reference signal to produce a periodic second reference signal, and

controller means for receiving said first and second reference signals and for controlling said magnitude of said power supply signal so as to maintain a constant phase difference between said first and second reference signals.

2. The system in accordance with claim 1 wherein said delay means is a passive delay line.

3. The system in accordance with claim 1 wherein a delay provided by said delay means is substantially independent of a temperature of said IC and of said magnitude of said power supply signal.

4. The system in accordance with claim 3 wherein a delay provided by said delay means is substantially larger than a signal path delay though said gate means.

5. The system in accordance with claim 3 wherein a signal path through said delay circuit is formed by a plurality of second transistors, wherein a phase difference between said first and second reference signals is a function of said magnitude of said power supply signal applied to said IC.

6. The system in accordance with claim 5 further comprising adjusting means for selectively adjusting a number of said second transistors in said signal path through said delay circuit.

7. The system in accordance with claim 6 wherein said adjusting means includes means for receiving and storing input data for controlling said number of second transistors included in said signal path through said delay circuit.

8. The system in accordance with claim 1 where said IC is a programmable logic device.

9. The system in accordance with claim 1 where said IC is a field programmable gate array (FPGA) including a plurality of logic blocks including said first transistors and interconnected to one another to form said signal path and said delay circuit in a manner controlled by input data.

10. The system in accordance with claim 1 wherein said controller means comprises a delay lock loop controller.

11. The system in accordance with claim 1 wherein said first and second reference signals have a 50% duty cycle.

12. A system for stabilizing a delay through a signal path of an integrated circuit (IC), wherein said signal path is formed by first transistors, wherein said delay depends on signal propagation speed of said first transistors which is in turn influenced by a magnitude of a power supply signal applied to said IC, the system comprising:

a first oscillator for producing a periodic first reference signal, wherein a period of said first reference signal is substantially independent of a temperature of said IC and of the magnitude of said power supply signal,

a second ring oscillator implemented on said IC for producing a periodic second reference signal, wherein a period of said second reference signal is a function of the temperature of said IC and the magnitude of said power supply signal; and

controller means for receiving said first and second reference signals and for controlling the magnitude of said power supply signal so as to maintain a constant phase difference between said first and second reference signals,

wherein said first oscillator comprises gate means internal to said IC having an input and an output and delay means external to said IC for connecting said input to said output.

13. The system in accordance with claim 12 wherein said delay means is a passive delay line.

14. The system in accordance with claim 12 wherein said second ring oscillator is formed by a plurality of second transistors, wherein a period of said second reference signal is a function of said magnitude of said power supply signal applied to said IC, and of a number of second transistors forming said second ring oscillator.

15. The system in accordance with claim 14 further comprising means for selectively adjusting the number of said second transistors forming said second ring oscillator.

16. The system in accordance with claim 12 where said IC is a programmable logic device.

17. The system in accordance with claim 12 where said IC is a field programmable gate array.