Battery polarity insensitive integrated circuit amplifier

• US 6,157,252 A
• Filed: 09/09/1998
• Issued: 12/05/2000
• Est. Priority Date: 09/09/1998
• Status: Expired due to Fees

• Current Assignee: The Engineering Consortium, Incorporated
• Original Assignee: The Engineering Consortium, Incorporated
• Inventors: Brown, Clyde "Kip "M. Jr., Compton, James Barclay
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/149,927
• Time in Patent Office: 818 Days
• Field of Search: 330/10, 330/207 A, 330/251, 330/297
• US Class Current: 330/10
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/3061 Bridge type, i.e. two complementary controlled SEPP output stages
• CPC Class Codes: H04R 2225/33 Aspects relating to adaptation of the battery voltage, e.g. its regulation, increase or decrease
• CPC Class Codes: H04R 25/602 of batteries

Abstract

A battery polarity insensitive amplifier utilizes a power management architecture to reduce the size of the circuitry used to accomplish the polarity correction function. An efficient Class D amplifier and compact voltage multiplying driver circuit reduce the size of the battery polarity insensitive amplifier circuit.

Claims

1. A Class D amplifier circuit powered by a voltage source, comprising:

a pulse width modulation control drive circuit for providing voltage multiplied in-phase and inverted pulse width modulated signals, said drive circuit including a pulse trimming apparatus which generates said in-phase and inverted pulse width modulated signals; and

a plurality of transistors arranged in an H-bridge configuration, each of said transistors having a gate;

wherein the gates of the transistors of the H-bridge are interconnected such that they act in response to said in-phase signal and said inverted pulse width modulated signal to produce amplified pulse width modulated signals.

23. The amplifier of claim 1, wherein said pulse trimming apparatus reduces the width of said in-phase and phase-inverted pulse width modulated signals relative to each other such that there is substantially no temporal overlap between said in-phase and said inverted pulse width amplified signals.

24. The amplifier of claim 23, wherein said pulse trimming apparatus reduces the width of the pulses at least five nanoseconds with respect to each other.

25. The amplifier of claim 1, wherein said control drive circuit further includes a transient voltage pulse multiplier to increase the effective voltage of said pulse width modulated signals to at least twice the source voltage.

26. The amplifier of claim 25, wherein said transient voltage pulse multiplier comprises a charge pump circuit utilizing a capacitor having a silicon dioxide sandwich structure wherein at least one silicon dioxide layer is less than about 200 Å

in thickness and the voltage on each said capacitor is kept substantially below the electron tunneling voltage of the thinnest silicon dioxide layer.

27. The amplifier of claim 25, wherein said transient voltage pulse width multiplier comprises a charge pump circuit utilizing a capacitor comprising a silicon dioxide layer less than about 100 Å

in thickness interposed between a polysilicon layer and a conductive n-type surface layer disposed in a p-substrate layer and the capacitor being biased to reduce the parasitic varactor capacitance between said n-type surface layer and said p-type substrate.

28. The amplifier of claim 25, wherein said transient voltage pulse multiplier comprises capacitors with a substantially larger capacitance per unit area than the gates of said n-channel transistors.

29. The amplifier of claim 1, wherein said voltage source comprises a battery and said H-bridge is the output stage of said amplifier which is powered directly by said battery.

2. A Class D amplifier circuit powered by a voltage source, comprising:

a control drive circuit for providing voltage multiplied in-phase and inverted pulse width modulated signals, said control drive circuit reduces the width of said in-phase and phase-inverted pulse width modulated signals relative to each other such that there is substantially no temporal overlap between the in-phase and inverted pulse width amplified signals; and

a plurality of n-channel transistors arranged in an H-bridge configuration, each of said transistors having a gate;

wherein the gates of said transistors are interconnected such that they act in response to said in-phase signal and said inverted pulse width modulated signal to produce amplified pulse width modulated signals.

3. The amplifier of claim 2, wherein the control drive circuit reduces the width of the pulses at least five nanoseconds with respect to each other.

4. The amplifier of claim 2, wherein the drive circuit further includes a transient voltage pulse multiplier to increase the effective voltage of the pulse width modulated signals to at least twice the source voltage.

5. The amplifier of claim 4, wherein the transient voltage pulse multiplier comprises a charge pump circuit utilizing a capacitor having a silicon dioxide sandwich structure wherein at least one silicon dioxide layer is less than about 200 Angstroms in thickness and the voltage on each said capacitor is kept substantially below the electron tunneling voltage of the thinnest silicon dioxide layer.

6. The amplifier of claim 4, wherein the transient voltage pulse multiplier comprises a charge pump circuit utilizing a capacitor comprising a silicon dioxide layer less than about 100 Angstroms in thickness sandwiched between a polysilicon layer and a conductive n-type surface layer disposed in a p-substrate layer and the capacitor is biased to reduce the parasitic varactor capacitance between the n-type surface layer and the p-substrate.

7. The amplifier of claim 4, wherein said transient voltage pulse multiplier comprises capacitors with a substantially larger capacitance per unit area than the gates of said n-channel transistor switches.

8. The amplifier of claim 7, wherein the capacitance per unit area of the capacitors is greater than about 2 femto-farads per square microns, the capacitance per unit area of the gates of the n-channel transistor switches is less than about 0.15 femto-farads per square micron, and the gate length of said transistors is less than about 2.0 microns.

9. The amplifier of claim 8, wherein the capacitance per unit area of the capacitors is about four femto-farads per square micron, the capacitance per unit area of the gates is about 0.08 femto-farads per square micron, and the gate length is less than about 1.5 microns.

22. The amplifier of claim 4, wherein said drive circuit further includes at least two voltage multipliers, each of said voltage multipliers coupled to anti-phase signals generated from a phase splitter.

10. An integrated circuit Class D amplifier powered by a miniature battery of either polarity, comprising:

a constant polarity voltage source comprising a voltage polarity correction circuit powered by said battery and producing a constant polarity output voltage across two terminals, a polarity control circuit acting in response to battery inputs and reference signals from at least one of the terminals of said polarity corrected voltage source to produce control signals and at least one polarity adjustable voltage source powered by said battery, said polarity adjustable voltage source acting in response to control signals from said polarity control circuit to produce an adjusted polarity voltage output;

a pulse width modulation circuit for producing pulse width modulated pulses from input audio signals, said pulse width modulation circuit powered by said constant polarity voltage source;

a control drive circuit for providing voltage multiplied in-phase and inverted pulse width modulated signals, said drive circuit comprising transient voltage multipliers to increase the voltage of pulse width modulated signals to at least twice the source voltage, said pulse width modulated control drive circuit powered by said constant polarity voltage source;

four n-channel MOSFET transistor switches having a gate node, said switches powered by said battery and arranged in an H-bridge configuration;

wherein the gate nodes of the transistors of the H-bridge are interconnected such that they act in response to said in-phase signal and said inverted pulse width modulated signal to produce amplified pulse width modulated signals.

11. The Class D amplifier of claim 10, wherein the transient voltage pulse multiplier comprises a charge pump circuit utilizing capacitors having a silicon dioxide sandwich structure wherein at least one silicon dioxide layer is less than about 200 Angstroms in thickness and the voltage on each said capacitor is kept substantially below the electron tunneling voltage of the thinnest silicon dioxide layer.

12. The Class D amplifier of claim 10, wherein the transient voltage pulse multiplier of said drive circuit comprises a charge pump circuit utilizing at least one capacitor, said capacitor comprising a silicon dioxide layer less than about 100 Angstroms in thickness sandwiched between a polysilicon layer and a conductive n-type surface layer disposed on a p-substrate layer and said capacitor is biased to reduce the parasitic varactor capacitance between the n-type layer and the substrate.

13. The Class D amplifier of claim 10, wherein the transient voltage pulse multiplier comprises a charge pump circuit utilizing at least one capacitor, wherein the capacitance per unit area of the capacitors of said transient voltage pulse multiplier of said drive circuit is substantially larger than the capacitance per unit area of the gates of said n-channel transistor switches.

14. The amplifier of claim 13, wherein the capacitance per unit area of the capacitors is greater than about 3 femto-farads per square microns, the capacitance per unit are of the gates of said n-channel transistor switches is less than about 0.12 femto-farads per square micron, and the gate length of said n-channel transistor switches is less than about 2.0 microns.

15. The amplifier of claim 13, wherein the capacitance per unit area of the capacitors is about four femto-farads per square micron, the capacitance per unit area of the gates of said n-channel transistor switches is about 0.08 femto-farads per square micron, and the gate length of said n-channel transistor switches is less than about 1.5 microns.

16. The integrated circuit of claim 10, wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.

17. The integrated circuit of claim 11, wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.

18. The integrated circuit of claim 12, wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.

19. The integrated circuit of claim 13 wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.

20. The integrated circuit of claim 14, wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.

21. The integrated circuit of claim 15, wherein the pulses of said first signal of said driver and said pulses of said second signal of said driver are reduced in width by at least 5 nanoseconds with respect to each other such that there is at least a ten nanosecond delay between the pulses of said first signal and said second signal.