Method of implementing an accelerated graphics port for a multiple memory controller computer system
First Claim
1. A method of manufacturing a multiple memory controller computer comprising:
- providing at least two memory controllers for controlling a main memory wherein only a first one of the at least two memory controllers is connected to an accelerated graphics processor, wherein a second one of the at least two memory controllers is adapted for connection to at least one processing unit, and wherein each of the at least two memory controllers is independently and separately connected to a central processing unit (CPU) bus, a peripheral component interface (PCI) bus, and the main memory; and
connecting at least one configuration register to the first one of the at least two memory controllers, wherein said at least one configuration register defines a group of addresses in the main memory that are preferentially used over other addresses for storage of graphics data for accelerated graphics port transactions.
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Abstract
An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions. In a third embodiment of the invention, a plurality of memory controllers implemented on a single chip each contain an AGP and a set of configuration registers identifying a range of addresses that are preferably used for AGP transactions.
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Citations
25 Claims
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1. A method of manufacturing a multiple memory controller computer comprising:
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providing at least two memory controllers for controlling a main memory wherein only a first one of the at least two memory controllers is connected to an accelerated graphics processor, wherein a second one of the at least two memory controllers is adapted for connection to at least one processing unit, and wherein each of the at least two memory controllers is independently and separately connected to a central processing unit (CPU) bus, a peripheral component interface (PCI) bus, and the main memory; and connecting at least one configuration register to the first one of the at least two memory controllers, wherein said at least one configuration register defines a group of addresses in the main memory that are preferentially used over other addresses for storage of graphics data for accelerated graphics port transactions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of using a multiple memory controller system comprising:
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storing a graphical address remapping table in a main memory on a computer system having at least two memory controllers for controlling a main memory, wherein a selected one of the at least two memory controllers has at least one configuration register that defines a group of addresses in the main memory that are preferentially used over other addresses for storage of graphics data for accelerated graphics port transactions and wherein each of said at least two memory controllers is independently and separately connected to a central processing unit (CPU) bus, a peripheral component interface (PCI) bus, and the main memory; connecting a graphics accelerator to the selected one of the at least two memory controllers; storing a graphics address relocation table in a memory connected to the selected one of the at least two memory controllers; and accessing graphics data through the selected one of the at least two memory controllers. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A method of using a multiple memory controller system having a main memory, at least two memory controllers for controlling a main memory, and a graphics accelerator that is connected to a selected one of the at least two memory controllers, wherein each of said at least two memory controllers is independently and separately connected to a central processing unit (CPU) bus, a peripheral component interface (PCI) bus, and the main memory, the method comprising:
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storing a graphical address remapping table in the main memory, wherein the selected memory controller has a base register and a range register, wherein the base register defines the starting address of main memory that is available preferentially used over other addresses for storage of graphics data for accelerated graphics port transactions, and wherein the range register defines a group of addresses following the address referenced by the base register that are available for accelerated graphics port transactions; and programming an operating system to preferentially use addresses in the group defined by the base and range registers over other addresses for storage of graphics data when allocating main memory space for accelerated graphics port transactions. - View Dependent Claims (24)
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25. A method of manufacturing a multiple memory controller computer, the method comprising:
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providing at least two memory controllers and at least two main memories, wherein a selected one of the at least two memory controllers is connected to one of the at least two main memories, wherein each of the non-selected ones of the at least two memory controllers is connected to another of the at least two main memories, and wherein each of the at least two memory controllers is independently and separately connected to a central processing unit (CPU) bus and a peripheral component interface (PCI) bus; providing at least one configuration register connected to the selected one of the at least two memory controllers, wherein the at least one configuration register defines a group of addresses that are available for accelerated graphics port transactions; and configuring the at least two main memories as non-symmetric, with the one of the at least two main memories connected to the selected one of the at least two memory controllers preferentially used for accelerated graphics port transactions.
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Specification