Nonvolatile memory system, semiconductor memory, and writing method

• US 6,157,573 A
• Filed: 12/21/1999
• Issued: 12/05/2000
• Est. Priority Date: 07/09/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US09/468,329
• Time in Patent Office: 350 Days
• Field of Search: 365/185.24, 365/185.18, 365/185.21, 365/185.22, 365/185.28, 365/185.29
• US Class Current: 365/185.24
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A nonvolatile memory system comprising:

a plurality of nonvolatile memories;

a controller; and

a terminal,

wherein each of said plurality of nonvolatile memories includes;

a plurality of memory cells, each of which has a threshold voltage corresponding to data indicating one of a first state and a second state, wherein the threshold voltage corresponding to said first state is different from the threshold voltage corresponding to said second state, and

a plurality of word lines, each of which is coupled with corresponding memory cells of said plurality of memory cells,

wherein said controller controls a write operation in response to one command, and

wherein, in said write operation, the threshold voltages of memory cells coupled to a selected word line are collectively moved in a predetermined direction, and thereafter, threshold voltages of memory cells of said first state coupled to said selected word line are returned to a first state, and a threshold voltage of at least one memory cell of a second state coupled to said selected word line is put to said first state.

2. The nonvolatile memory system according to claim 1, wherein said threshold voltage exists within a voltage range having a first region indicating said second state and a second region indicating said first state.

3. The nonvolatile memory system according to claim 2, wherein said predetermined direction is toward said first region from said second region.

4. The nonvolatile memory system according to claim 3, wherein said threshold voltage of a memory cell of said first state coupled to said selected word line is moved between said first and second regions by execution of said one command.

5. The nonvolatile memory system according to claim 3, wherein said threshold voltage of a memory cell of said first state coupled to said selected word line is moved to said first region by execution of said one command.

6. The nonvolatile memory system according to claim 1,

wherein said first state corresponds to a written state and said second state corresponds to an erased state.

7. A nonvolatile memory system comprising:

a plurality of nonvolatile memories;

a terminal; and

a controller,

wherein each of said plurality of nonvolatile memories includes a plurality of memory cells, each of which has a threshold voltage corresponding to data,

wherein said controller controls a threshold voltage of a memory cell in response to a command, and

wherein, in response to a command indicating an additional write operation, said controller controls a data synthesizing operation of data read from selected memory cells of said plurality of memory cells and of data supplied from said terminal, and controls a writing operation for writing a synthesized data obtained by said data synthesizing operation to said selected memory cells.

8. The nonvolatile memory system according to claim 7, further comprising a rewriting circuit forming said synthesized data.

9. The nonvolatile memory system according to claim 8, further comprising a plurality of word lines, each of which is coupled with corresponding memory cells of said plurality of memory cells.

10. A nonvolatile memory system comprising:

a terminal;

a controller; and

a plurality of nonvolatile memories, each nonvolatile memory including a plurality of memory cells, each memory cell having a threshold voltage corresponding to data;

wherein each nonvolatile memory further includes a voltage generating circuit generating an erase voltage under control by said controller, and a sense latch circuit storing data supplied from said terminal and data read from selected memory cells;

wherein said controller controls a threshold voltage of a memory cell in response to a command, and

wherein, in response to a command indicating an additional write operation, synthesized data of data read from selected memory cells of said plurality of memory cells and of data supplied from said terminal are stored in said sense latch circuits, and said selected memory cells are written in accordance with said synthesized data stored in said sense latch circuits after said selected memory cells are supplied with said erase voltage in a predetermined time under control by said controller.

11. The nonvolatile memory system according to claim 10, further comprising a plurality of data lines, wherein each of said plurality of data lines is coupled with corresponding memory cells and with said sense latch circuit.

12. The nonvolatile memory system according to claim 11, further comprising a rewriting circuit, wherein said rewriting circuit is coupled to said plurality of data lines and forms said synthesized data from said read data and said supplied data from said terminal.

13. The nonvolatile memory system according to claim 12, further comprising a plurality a word lines, each of which is coupled with corresponding memory cells of said plurality of memory cells.

14. The nonvolatile memory system according to claim 13, further comprising a decoder decoding address signals and selecting a word line from said plurality of word lines.

15. The nonvolatile memory system according to claim 14, wherein the time during which said erase voltage is supplied to said selected memory cells by said command indicating said additional write operation is shorter than the time during which said erase voltage is supplied to selected memory cells by a command indicating an erase operation.

16. A nonvolatile memory system comprising:

a plurality of nonvolatile memories; and

a controller controlling a predetermined operation in response to a command supplied thereto,

wherein each of said plurality of nonvolatile memories has a plurality of memory cells, each memory cell having a threshold voltage corresponding to data of a first state and a second state, wherein the threshold voltage corresponding to said first state is different from the threshold voltage corresponding to said second state, and each of said nonvolatile memories having a plurality of word lines, each of which is coupled with corresponding memory cells of said plurality of memory cells,

wherein said controller controls an erase operation to erase data of selected memory cells coupled to a word line when an erase command is supplied to said controller,

wherein said controller controls a write operation to write data to a memory cell of said memory cells coupled to said word line when a write command is supplied to said controller,

wherein said controller controls an additional write operation to write data to a memory cell of said second state in a word line coupled with memory cells of said write and said second state when an additional write command is supplied to said controller,

wherein, in said erase operation, threshold voltages of memory cells coupled to a word line are allocated to said second state by using a tunnel phenomenon; and

wherein, in said write and said additional write operation, a threshold voltage of a memory cell is allocated to said first state by using a tunnel phenomenon.

17. The nonvolatile memory system according to claim 16, wherein each of said plurality of nonvolatile memories includes a circuit which forms a write expected value data based on data read from memory cells coupled to a selected word line and additional write data supplied from outside.

18. The nonvolatile memory system according to claim 17, wherein each of said plurality of nonvolatile memories includes a data register which stores data to be written to a memory cell coupled to a selected word line, and wherein, in an additional write operation, said data register stores said write expected value data.

19. The nonvolatile memory system according to claim 18, wherein each of said plurality of nonvolatile memories includes a plurality of data lines, each of which is coupled with corresponding memory cells, and wherein said data register is coupled to said plurality of data lines.

20. The nonvolatile memory system according to claim 16,

wherein said first state corresponds to a write state and said second state corresponds to an erase state.