ATM communication system and ATM communication method

• US 6,157,645 A
• Filed: 05/28/1997
• Issued: 12/05/2000
• Est. Priority Date: 05/28/1996
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shobatake, Yasuro
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): NGUYEN, STEVEN H D
• Application Number:
  US08/870,425
• Time in Patent Office: 1,287 Days
• Field of Search: 370/392, 370/393, 370/395, 370/396, 370/398, 370/399, 370/400, 370/409, 370/420, 370/421, 370/422, 370/423, 370/433, 370/437, 370/439, 370/443, 370/447, 370/449, 370/451 , 370/458, 370/461-462, 370/463, 370/465, 370/466, 347/6-13, 345/347, 345/348, 345/352, 345/353, 710/370, 710/347, 710/345
• US Class Current: 370/395.41
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/5664 Support of Video, e.g. MPEG
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

An ATM cell transmission route is formed by hierarchically connecting a plurality of buses for connecting at least one first device and a plurality of second devices, and an ATM cell is to be transmitted from a first device designed to transmit/receive ATM cells and connected to one of the plurality of buses. The first device generates an ATM cell transmission message by inserting the ATM cell into a message in a format depending on the bus, and outputs an address for designating a device as the destination of the ATM cell transmission message by using a bus identifier for identifying one of the plurality of buses and a device identifier for identifying one of the plurality of devices. The ATM cell transmission message is then written in the device designated by the address. With this operation, an ATM communication system having a simple arrangement can be provided. In addition, ATM communication can be performed, with the QOS (quality of service) being guaranteed by priority control of an arbiter connected to one of the plurality of buses.

Claims

1. A communication system comprising:

a plurality of bus segments including at least one bandwidth aware bus segment and at least one bus segment other than said bandwidth aware bus segment;

at least one bridge circuit connecting between said bus segments;

a plurality of devices including at least one first device connecting with said bandwidth aware bus segment and at least one second device connecting with said bus segment; and

an arbiter provided on said bandwidth aware bus segment, wherein

said bandwidth aware bus segment is connected to said first device and said bridge circuit;

said first device comprises,

a message generating unit configured to generate an internal-bus message having a predetermined fix length message by adapting information to be transmitted into a form of the predetermined fix length message,

a bus request unit configured to output, to said arbiter, a bus request signal for requesting authorization to use said bandwidth aware bus segment so as to output the internal-bus message generated by said message generating unit,

an address output unit configured to output, when authorization to use said bandwidth aware bus segment is given by said arbiter which has received the bus request signal, an address for designating a device as a destination of the internal-bus message generated by said message generating unit, by using a bus identifier for identifying one of said plurality of bus segments and a device identifier for identifying one of said plurality of devices, and

a message transmission unit configured to transmit the internal-bus message to said device designated by the address output from said address output unit to write the internal-bus message in said device; and

said arbiter comprises,

a bus authorizing unit configured to give, when receiving the bus request signals from said first device and said bridge circuit, authorization to use said bandwidth aware bus segment to one of said first device and said bridge circuit, and

a band assigning unit configured to give, when receiving the bus request signal output from said first device, authorization to use said bandwidth aware bus segment to said first device in accordance with an interval during which the predetermined fix length message is sent and which is calculated on the basis of bandwidth assigned to said first device in advance.

2. A communication system according to claim 1, wherein said address output includes a section configured to provide a header including the address on the internal-bus message.

3. A communication system according to claim 1, wherein said bus segments are constructed by PCI bus segments and said message transmission unit includes a transmission unit configured to perform a transmission of the message in a form of a write cycle.

4. A communication system comprising:

a first-level bus segment connected to a microprocessor;

a bus bridge;

a second-level bus segment connected to said first-level bus segment via said bus bridge;

a plurality of devices connected to said first-level bus segment;

a plurality of bandwidth-aware devices connected to said second-level bus segment; and

a bandwidth-aware arbiter giving authorization to use said second-level bus segment to said bandwidth-aware devices;

wherein said bandwidth-aware devices each comprise,

a message generating unit configured to generate an internal-bus message having a predetermined fix length message by adapting information to be transmitted into a form of the predetermined fix length message and inserting the predetermined fix length message to be transmitted to one of said devices into a message in a format depending on said first-level bus segment and said second-level bus segment,

a bus request unit configured to output, to said bandwidth aware arbiter, a bus request signal for requesting authorization to use said second-level bus segment so as to output the internal-bus message generated by said message generating unit,

an address output unit configured to output, when authorization to use one of said bus segments is given by said arbiter which has received the bus request signal, an address for designating a device as a destination of the internal-bus message generated by said message generating unit, by using a bus identifier for identifying one of said plurality of bus segments and a device identifier for identifying one of said plurality of devices, and

a message transmission unit configure to transmit the internal-bus message to said device designated by the address output from said address output unit to write the internal-bus message in said device; and

wherein said bandwidth-aware arbiter comprises,

a bus authorizing unit configured to give, when receiving bus request signals from said bandwidth-aware device and said bus bridge, authorization to use said second-level bus segment to said bandwidth-aware device in preference to said bus bridge, and

a band assigning unit configured to give, when receiving a bus request signal output from said bandwidth-aware device, authorization to use said second-level bus segment to said bandwidth-aware device in accordance with an interval during which the predetermined fix length message is sent and which is calculated on the basis of bandwidth assigned to said devices by said microprocessor in advance.