Hub port with constant phase

• US 6,157,652 A
• Filed: 05/01/1998
• Issued: 12/05/2000
• Est. Priority Date: 05/01/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Emulex Corporation (Broadcom, Inc.)
• Inventors: Hashemi, Hossein, Brewer, David, Henson, Karl M.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Previl, Daniel
• Application Number:
  US09/071,932
• Time in Patent Office: 949 Days
• Field of Search: 370/407, 370/403, 370/404, 370/405, 370/406, 370/424, 370/503, 370/507, 370/516
• US Class Current: 370/407
• CPC Class Codes: H04J 3/062 Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers pulse-stuffing H04J3/07; asynchronous-synchronous conversion H04L5/24; speed conversion H04L25/05; speed conversion in computers G06F5/06
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 12/44 Star or tree networks
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A hub port which maintains a constant phase in a datastream and reduces jitter transfer to an attached node port. The hub port includes circuitry for maintaining constant bit boundaries for all data transmitted along the hub loop from that hub port using an internal clock. In addition, the internal clock is used to reduce jitter transfer.

Claims

1. A hub port for connecting a hub to a node port, where the hub includes at least two hub ports interconnected in a loop with internal hub links, the hub port comprising:

(a) a hub clock line connected to a local clock internal to the hub for supplying a local clock signal;

(b) a multiplexer which includes a first data input, a second data input, a third data input, and a control input;

(c) a hub output register connected to the multiplexer, and to the hub clock line;

(d) an incoming internal hub link connected to the third data input of the multiplexer;

(e) an outgoing internal hub link connected to the hub output register;

(f) a transmit circuit connected to the incoming internal hub link and to the hub clock line;

(g) an encoder connected to the transmit circuit and to the hub clock line;

(h) a current fill word generator connected to the second data input of the multiplexer and to the hub clock line;

(i) a fill word detect circuit connected to the current fill word generator;

(j) a smoothing buffer connected to the first data input of the multiplexer, the current fill word generator, the fill word detect circuit, and to the hub clock line;

(k) a smoothing control circuit connected to the smoothing buffer;

(l) a hub port output control circuit connected to the smoothing control circuit and the control input of the multiplexer;

(m) a word synchronization detect circuit connected to the smoothing control circuit;

(n) a receive circuit connected to the word synchronization detect circuit and the smoothing buffer;

(o) a decoder connected to the receive circuit; and

(p) a serializer/deserializer circuit connected to the encoder, the decoder, the node port, and to the hub clock line, where the serializer/deserializer circuit includes a recovered clock output connected to the decoder, the word synchronization detect circuit, and the smoothing buffer.

2. The hub port of claim 1 where the smoothing buffer is a FIFO buffer.

3. The hub port of claim 1 where the encoder is a 8B/10B encoder.

4. The hub port of claim 1 where the decoder is a 10B/8B decoder.

5. The hub port of claim 1 where the local clock is contained in the hub port.

6. The hub port of claim 1 where the transmit circuit ensures that only full words of data are transmitted to the node port.

7. The hub port of claim 1 where the transmit circuit sends data to the node port using the local clock signal.

8. A method of maintaining constant phase in data output by a hub port for connecting a hub to a node port, where the hub includes at least two hub ports interconnected in a loop, the method comprising:

(a) sending data from the node port to the hub port;

(b) deserializing the data from the node port;

(c) recovering a recovered clock signal from the data from the node port;

(d) decoding the deserialized data;

(e) checking the decoded data for word synchronization;

(f) writing the decoded data to a buffer using the recovered clock signal;

(g) reading the decoded data from the buffer using a clock signal local to the hub;

(h) outputting the decoded data from the hub port;

(i) repeating steps (e) to (h) so long as the data received from the node port is word synchronized;

(j) while word synchronization is lost, outputting data from the hub port which is received from another hub port in the hub;

(k) when an amount of data in the buffer falls below a minimum threshold, outputting at least one current fill word from the hub port; and

(l) when the amount of data in the buffer exceeds a maximum threshold, deleting at least one fill word from the data stored in the buffer.

9. The method of claim 8 further comprising:

(a) synchronizing data from an upstream hub port to the local clock signal; and

(b) transmitting the synchronized data from the upstream hub port to the node port.