Method of and apparatus for multiplexing and demultiplexing digital signal streams

• US 6,157,659 A
• Filed: 12/19/1997
• Issued: 12/05/2000
• Est. Priority Date: 12/19/1997
• Status: Expired due to Fees

• Current Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Original Assignee: Nortel Networks Corporation
• Inventors: Bird, Peter Dane
• Primary Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/995,414
• Time in Patent Office: 1,082 Days
• Field of Search: 370/538, 370/532, 370/230, 370/231, 370/232, 370/235, 370/535, 370/537, 370/540, 370/505, 375/225, 375/371, 375/372, 375/364
• US Class Current: 370/538
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH
• CPC Class Codes: H04J 3/1641 Hierarchical systems

Abstract

Multiplexing and demultiplexing are commonplace for an efficient bandwidth utilization in telecommunications. SRTS (Synchronous Residual Time Stamp) technique is widely used for timing recovery in processing of digital signal streams. The bit stuffing is also prevalent for various purposes, one being rate adjustment. The invention performs the SRTS technique entirely digitally to monitor the rate of slower speed signal streams in relation to the rate of a higher speed stream. The digital implementation permits the use of context switching for processing a plurality of digital signal streams. As the result, hardware requirement is greatly reduced.

Claims

1. A multiplexer of a plurality of first signal streams into a second signal stream, the first signal streams having a substantially similar first rate and the second signal stream having a second rate higher than the first rate, comprising:

a buffer for buffering the first signal streams;

an SRTS circuit for receiving SRTS values of each first signal stream;

a local SRTS circuit for generating local SRTS values of each first signal stream based on a reference clock rate;

a stuffing circuit for stuffing the plurality of first signal streams in response to a stuff command signal which has been generated for each first signal stream in response to its respective sequences of SRTS values and local SRTS values; and

a combiner circuit for combining all the first signal streams into the second signal stream.

2. The multiplexer according to claim 1 further comprising:

the SRTS circuit including delta circuits for calculating a first difference of successive SRTS values;

the local SRTS circuit including local delta circuits for calculating a second difference of successive local SRTS values, and

a cumulative delta circuit for registering a cumulative value of a third difference between the first and second differences for each first signal stream.

3. The multiplexer according to claim 2 further comprising:

a stuff command circuit for generating the stuff command signal in response to the cumulative value of the third difference.

4. The multiplexer according to claim 1 further comprising:

a memory for storing instantiation values of the SRTS circuit, local SRTS circuit and stuffing circuit for each first signal stream, and

a processor for performing context switching the executions of the SRTS circuit, local SRTS circuit and the stuffing circuit for each first signal stream.

5. The multiplexer according to claim 3 further comprising:

a memory for storing instantiation values of the SRTS circuit, local SRTS circuit, delta SRTS circuits, delta local SRTS circuit, stuffing circuit, and stuff command circuit for each first signal stream, and

a processor for performing context switching the executions of the SRTS circuit, local SRTS circuit, delta SRTS circuits, delta local SRTS circuit, stuffing circuit, and stuff command circuit for each first signal stream.

6. The multiplexer according to claim 3 wherein the stuff command circuit comprises:

a stuff target circuit for comparing the cumulative value of the third difference and a target stuff ratio to generate the stuff command signal.

7. The multiplexer according to claim 5 wherein the first and second signal streams are chosen from any one group of the followings, DS1, DS2, and DS3, and E1, E2 and E3.

8. The multiplexer according to claim 6 wherein the first and second signal streams are chosen from any one group of the followings, DS1, DS2, and DS3, and E1, E2 and E3.