Dual priority chains for data-communication ports in a multi-port bridge for a local area network

• US 6,157,951 A
• Filed: 04/22/1998
• Issued: 12/05/2000
• Est. Priority Date: 09/17/1997
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Vasa, Suresh L.
• Primary Examiner(s): Harrell, Robert B.
• Application Number:
  US09/064,806
• Time in Patent Office: 958 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 709/200, 709/206, 709/207, 709/218, 709/225, 709/232, 709/238, 709/240, 709/249, 709/251
• US Class Current: 709/223
• CPC Class Codes: H04L 12/18 for broadcast or conference , e.g. multicast
• CPC Class Codes: H04L 12/462 LAN interconnection over a bridge based backbone
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/135 by jamming the transmission media
• CPC Class Codes: H04L 47/30 in combination with information about buffer occupancy at either end or at transit nodes
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/521 Static queue service slot or fixed bandwidth allocation
• CPC Class Codes: H04L 47/56 implementing delay-aware scheduling
• CPC Class Codes: H04L 47/6215 Individual queue per QOS, rate or priority
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9073 Early interruption upon arrival of a fraction of a packet

Abstract

A technique for prioritizing accesses to a communication bus by data-communication ports in a multi-port bridge for a local area network. The bridge includes a plurality of ports interconnected by the bus. The bus includes signal lines dedicated to communicating commands, signal lines dedicated to communicating data, and several signal lines having special purposes. For example, two signal lines, are preferably dedicated to initiating different types of access to the bus, each having a respective priority. The ports are of two types (e.g. 100 Mbps or 10 Mbps data rates), each having a respective priority. A bus controller monitors the type of access to the bus attempted and the type of ports attempting access and grants access to the bus according to an appropriate priority. Ports of a like type which attempt a like type of access to the communication bus are granted access to the bus according to an assigned relative order, wherein the assigned relative order repeats and wherein a port last granted access to the communication bus has a lowest priority and a port adjacent in the assigned relative order to the last port granted access to the communication bus has a highest priority and remaining ports have ascending intermediate levels of priority according to the assigned relative order. Logic utilized makes a determination of which port is to be granted access to the bus in the appropriate priority with a minimum of delay.

Claims

1. An apparatus for granting access to a communication bus, the communication bus for interconnecting a plurality of ports in a multi-port bridge for a local area network, the apparatus comprising:

a. a first plurality of signal lines, one signal line for each port of a first plurality of ports wherein a logic level applied to the signal line for each port of the first plurality is indicative of whether the corresponding port is attempting access to the communication bus; and

b. a first chain circuit coupled to the first plurality of signal lines for determining which of the first plurality of ports is to be granted access to the communication bus, wherein the first chain circuit comprises a first plurality of links, one link for each of the first plurality of ports, wherein each link is selectively configured for passing a first logic signal to a next link according to the logic level of the signal line of the port corresponding to the link.

2. The apparatus according to claim 1 wherein the first chain circuit is coupled to receive a first enable signal and wherein the first logic signal originates in response to the first enable signal.

3. The apparatus according to claim 2 wherein the first enable signal is formed in response to one or more of the first plurality of ports attempting a first type of access to the communication bus.

4. The apparatus according to claim 3 further comprising a second chain circuit coupled to the first plurality of signal lines for determining which of the first plurality of ports is to be granted access to the communication bus, wherein the second chain circuit comprises a second plurality of links, one link for each of the first plurality of ports, wherein each link is selectively configured for passing a second logic signal to a next link according to the logic level of the signal line of the port corresponding to the link.

5. The apparatus according to claim 4 wherein the second chain circuit is coupled to receive a second enable signal and wherein the second logic signal originates in response to the second enable signal.

6. The apparatus according to claim 5 wherein the second enable signal is formed in response to one or more of the second plurality of ports attempting a second type of access to the communication bus.

7. The apparatus according to claim 6 wherein the first and second type of access to the communication bus each have a relative priority for access the communication bus.

8. The apparatus according to claim 6 wherein the first chain circuit forms a first output signal for each port of the first plurality and wherein the second chain circuit forms a second output for each port of the first plurality and wherein the first output signal and the second output signal for each port are combined according to a logic OR function.

9. The apparatus according to claim 2 further comprising:

a. a second plurality of signal lines, one signal line for each port of a second plurality of ports wherein a logic level applied to the signal line for each port of the second plurality is indicative of whether the corresponding port is attempting access to the communication bus; and

b. a second chain circuit coupled to the second plurality of signal lines for determining which of the second plurality of ports is to be granted access to the communication bus, wherein the second chain circuit comprises a second plurality of links, one link for each of the second plurality of ports, wherein each link is selectively configured for passing a second logic signal to a next link according to the logic level of the signal line of the port corresponding to the link.

10. The apparatus according to claim 9 wherein the second chain circuit is coupled to receive a second enable signal and wherein the second logic signal originates in response to the second enable signal.

11. The apparatus according to claim 10 wherein the first enable signal is formed in response to one or more of the first plurality of ports attempting to access the communication bus and wherein the second enable signal is formed in response to one or more of the second plurality of ports attempting to access the communication bus.

12. The apparatus according to claim 11 wherein the first plurality of ports and second plurality of ports each have a relative priority for accessing the communication bus.

13. The apparatus according to claim 11 wherein the first chain circuit forms a first output signal for each port of the first plurality and wherein the second chain circuit forms a second output for each port of the second plurality.

14. The apparatus according to claim 1 wherein the first plurality of links are coupled to form a loop.

15. The apparatus according to claim 1 wherein the first logic signal originates in a link adjacent to a link corresponding to a port of the first plurality last granted access to the communication bus.

16. An apparatus for granting access to a communication bus, the communication bus for interconnecting a plurality of ports in a multi-port bridge for a local area network, the apparatus comprising:

a. a plurality of signal lines, one signal line for each port of the plurality;

b. a first circuit coupled to each of the plurality of ports for determining a type of access to the communication bus;

c. a second circuit coupled to each of the signal lines for determining a type of port attempting access to the communication bus; and

d. a third circuit coupled to the first circuit and to the second circuit for determining which of the plurality of ports is to be granted access to the communication bus, wherein ports of a like type which attempt a like type of access to the communication bus are granted access to the communication bus according to an assigned relative order wherein a port last granted access to the communication bus has a lowest priority and a port adjacent in the assigned relative order to the last port granted access to the communication bus has a highest priority and remaining ports have ascending intermediate levels of priority according to the assigned relative order.

17. The apparatus according to claim 16 wherein the first circuit comprises a first logic AND gate having a first input, a second input and an output wherein the first input is coupled to receive a first signal representative of whether any of the plurality of ports is attempting a first type of access and the second input is coupled to receive a signal representative of whether any of the plurality of ports is attempting a second type of access.

18. The apparatus according to claim 17 wherein the second circuit comprises a second logic AND gate having a first input, a second input and an output wherein the first input is coupled to receive a signal representative of whether any of a first type of port of the plurality of ports is attempting to access the communication bus and the second input is coupled to receive a signal representative of whether any of a second type of port of the plurality of ports is attempting to access the communication bus.

19. The apparatus according to claim 18 wherein the third circuit comprises:

a. a first logic circuit coupled to the output of the first logic AND gate and coupled to the output of the second logic AND gate, the first logic circuit for forming a plurality of enable signals; and

b. a plurality of chain encoder circuits coupled to the first logic circuit and to the plurality of signal lines, one chain encoder circuit for each enable signal, and each chain encoder circuit having a plurality of links, one link for each port serviced by the chain encoder circuit, wherein each link of each chain encoder circuit is selectively configured for passing a logic signal to a next link according to a logic level of the signal line of the port corresponding to the link.

20. The apparatus according to claim 16 wherein the second circuit comprises a second logic AND gate having a first input, a second input and an output wherein the first input is coupled to receive a signal representative of whether any of a first type of port of the plurality of ports is attempting to access the communication bus and the second input is coupled to receive a signal representative of whether any of a second type of port of the plurality of ports is attempting to access the communication bus.

21. The apparatus according to claim 16 wherein a logic level applied to the signal line for each port is indicative of whether the corresponding port is attempting access to the communication bus.

22. The apparatus according to claim 21 wherein the third circuit is coupled to receive the logic level applied to the signal line for each port and further wherein the third circuit determines which port of the plurality is to be granted access to the bus within a single cycle of a bus clock after the third circuit receives each logic level.

23. The apparatus according to claim 16 wherein the assigned relative order repeats.

24. The apparatus according to claim 16 wherein the communication bus comprises the signal lines.

25. The apparatus according to claim 16 wherein the type of port is selected according a rate which the port transmits and receives data.

26. The apparatus according to claim 16 wherein the type of attempt is selected from a look-up operation for determining a destination for an incoming packet and a memory transfer operation for transferring a packet between a memory device and a port of the plurality.

27. A method of granting access to a communication bus, the communication bus for interconnecting a plurality of ports in a multi-port bridge for a local area network, the method comprising steps of:

a. receiving one or more attempts for access to the communication bus from one or more of the ports wherein each attempt is one of a plurality of different types of attempts and each port is one of a plurality of different types of ports;

b. determining which of the plurality of ports is to be granted access to the communication bus, wherein each type of attempt has a relative priority and each type of port has a relative priority, wherein ports of a like type which attempt a like type of access to the communication bus are granted access to the communication bus according to an assigned relative order, wherein a port last granted access to the communication bus has a lowest priority and a port adjacent in the assigned relative order to the last port granted access to the communication bus has a highest priority and remaining ports have ascending intermediate levels of priority according to the assigned relative order.

28. The method according to claim 27 wherein the type of attempt is selected from a look-up operation for determining a destination for an incoming packet and a memory transfer operation for transferring a packet between a memory device and a port of the plurality.

29. The method according to claim 28 wherein a memory pointer for the packet is stored in the port.

30. The method according to claim 27 wherein the assigned relative order repeats.

31. The method according to claim 27 wherein the type of port is selected according a rate which the port transmits and receives data.

32. An apparatus for granting access to a communication bus, the communication bus for interconnecting a plurality of ports in a multi-port bridge for a local area network, the apparatus comprising:

a. means for collecting the plurality of ports into a plurality of groups of ports, wherein each group of ports has a predetermined relative group priority and the ports within each group of ports have a predetermined relative port order;

b. means for determining whether any one of the ports is requesting access to the communication bus;

c. means for determining a highest current group from among the groups of ports having a port requesting access to the communication bus according to the predetermined relative group priority;

d. means for determining when there is more than one port in the highest current group which is requesting access to the communication bus; and

e. means for granting access to an accessing requesting port of the highest current group according to the predetermined relative port order, wherein a port last granted access to the communication bus is a last port within the relative port order of the highest current group.

33. The apparatus according to claim 32 wherein a port adjacent in the predetermined relative port order to the last port granted access to the communication bus is a first port within the relative port order and remaining ports are intermediate ports according to the predetermined relative port order.

34. The apparatus according to claim 32 further comprising means for sequentially granting access to remaining access requesting ports within the highest current group according to the predetermined relative port order when more than one port of the highest current group is requesting access to the communications bus.

35. The apparatus according to claim 32 further comprising:

a. means for determining a type of each request from among a plurality of types of requests wherein each of the plurality of types of requests has a predetermined relative request priority; and

b. means for determining a highest current type of request from the plurality of types of requests according to the predetermined relative request priority;

wherein the means for determining the highest current group further comprises means for determining the highest current group from among the groups of ports having one or more ports requesting the highest current type of request and further wherein the access requesting port of the highest current group further comprises one of the ports requesting the highest current type of request.