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Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system

  • US 6,157,989 A
  • Filed: 06/03/1998
  • Issued: 12/05/2000
  • Est. Priority Date: 06/03/1998
  • Status: Expired due to Term
First Claim
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1. A bus master device for coupling to a shared memory via a common bus, the common bus adapted to couple to another bus master device, comprising:

  • an execution unit having an input terminal for receiving a current priority signal which indicates a degree of fullness of a memory segment located in the shared memory, and an output terminal coupled to an output terminal of the bus master device, said execution unit periodically arbitrating for usage of the common bus in response to an internal operation by providing said current priority signal to said output terminal; and

    a snoop logic block having an input terminal coupled to the common bus, and an output terminal coupled to said input terminal of said execution unit for providing said current priority signal thereto, wherein said snoop logic block monitors a fullness state of said memory segment and changes said current priority signal in response to the another bus master device accessing said memory segment.

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