Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof

• US 6,158,032 A
• Filed: 03/27/1998
• Issued: 12/05/2000
• Est. Priority Date: 03/27/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Douskey, Steven Michael, Ganfield, Paul Allen, Currier, Guy Richard, Day, Leland Leslie, Wallin, James Maurice
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/049,170
• Time in Patent Office: 984 Days
• Field of Search: 714/726, 714/727, 714/729, 324/73.1, 324/763
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

Claims

1. A circuit arrangement, comprising:

(a) first and second scan ring segments, each scan ring segment including an input and an output; and

(b) a multiplexer, coupled between the first and second scan ring segments, the multiplexer configured to selectively couple the output of the first scan ring segment to the input of the second scan ring segment, wherein in a first mode, the first and second scan ring segments operate in a common scan path, and in a second mode, the first and second scan ring segments operate in separate scan paths.

2. The circuit arrangement of claim 1, wherein the multiplexer includes first and second inputs and an output.

3. The circuit arrangement of claim 2, wherein the input of the first scan ring segment is configured to receive a first scan in signal, wherein the first input of the multiplexer is coupled to the output of the first scan ring segment, the output of the multiplexer is coupled to the input of the second scan ring segment, and the second input of the multiplexer is configured to receive a second scan in signal, wherein the multiplexer is configured to selectively operate in one of the first and second modes in response to a select signal, and wherein in the first mode the multiplexer couples the first input of the multiplexer to the output of the multiplexer, and in the second mode the multiplexer couples the second input of the multiplexer to the output of the multiplexer.

4. The circuit arrangement of claim 3, further comprising a second multiplexer, interposed between the first scan ring segment and the first multiplexer.

5. The circuit arrangement of claim 4, wherein the second multiplexer includes first and second inputs and an output, the first input of the second multiplexer coupled to the output of the first scan ring segment, the output of the second multiplexer coupled to the first input of the first multiplexer, and the second input of the second multiplexer configured to receive a third scan in signal.

6. The circuit arrangement of claim 4, wherein the second multiplexer includes first and second inputs and an output, the first input of the second multiplexer coupled to the output of the first scan ring segment, the second input of the second multiplexer coupled to the input of the first scan ring segment, and the output of the second multiplexer coupled to the first input of the first multiplexer, wherein the second multiplexer is configured to selectively operate in one of first and second modes in response to a second select signal, wherein in the second mode the second multiplexer couples the second input of the second multiplexer to the output of the second multiplexer and thereby bypasses the first scan ring segment.

7. The circuit arrangement of claim 4, further comprising a third multiplexer interposed between the output of the first scan ring segment and the second multiplexer.

8. The circuit arrangement of claim 3, further comprising:

(a) a first logic gate including first and second inputs and an output, the first and second inputs of the first logic gate respectively configured to receive a parallel scan mode signal and an external scan mode signal, and the output of the first logic gate coupled to the first multiplexer to provide the select signal thereto, wherein the first multiplexer is configured to operate in the first mode in response to assertion of the parallel scan mode signal and deassertion of the external scan mode signal;

(b) a second and third multiplexers, each including first and second inputs and an output, the first input of the second multiplexer coupled to the output of the first scan ring segment, the second input of the second multiplexer coupled to the input of the first scan ring segment, the output of the second multiplexer coupled to the first input of the third multiplexer, the second input of the third multiplexer configured to receive a third scan in signal, and the output of the third multiplexer coupled to the first input of the first multiplexer, wherein the third multiplexer is configured to pass the third scan in signal to the first input of the first multiplexer in response to assertion of the external scan mode signal; and

(c) a second logic gate including first, second and third inputs and an output, the first and second inputs of the second logic gate respectively configured to receive the parallel scan mode signal and the external scan mode signal, the third input of the second logic gate configured to receive a scan group select signal, and the output of the second logic gate configured to output a select signal to the second multiplexer such that the second multiplexer couples the output of the first scan ring segment to the first input of the third multiplexer in response to assertion of any of the parallel scan mode signal, the external scan mode signal, and the scan group select signal.

9. The circuit arrangement of claim 3, further comprising a reset circuit arrangement, configured to respectively provide first and second flush signals to the input of the scan ring segment and the second input of the multiplexer, the reset circuit arrangement configured to configure the multiplexer in the second mode such that the first and second flush signals are concurrently scanned into the first and second scan ring segments.

10. The circuit arrangement of claim 3, wherein the first and second scan ring segments are respectively configured to generate first and second scan out signals at the outputs thereof, the circuit arrangement further comprising:

(a) a pseudo-random pattern generator including first and second channels respectively configured to supply the first and second scan in signals to the first and second scan ring segments; and

(b) a multiple input shift register including first and second channels respectively configured to receive the first and second scan out signals from the first and second scan ring segments.

11. The circuit arrangement of claim 10, further comprising a channel select multiplexer including first and second inputs coupled to the first and second channels of the multiple input shift register, the channel select multiplexer further including an output configured to output one of the first and second scan out signals in response to a channel select signal.

12. The circuit arrangement of claim 1, further comprising a service interface coupled to the multiplexer and the first and second scan ring segments, the service interface including a service access port coupled to the first and second scan ring segments.

13. The circuit arrangement of claim 12, wherein the service interface includes a test access port controller, the test access port controller including a test data input/output partition configured to receive a test data in signal from the service access port and provide the test data in signal as the first scan in signal, and to output a test data out signal through the service access port using the scan out signal.

14. The circuit arrangement of claim 12, further comprising a clock distribution circuit arrangement configured to supply at least one clock signal to the first and second scan ring segments, the clock distribution circuit arrangement configured to receive a service interface clock signal from the service interface and a functional clock signal.

15. The circuit arrangement of claim 14, further comprising first and second cores, wherein the clock distribution circuit arrangement includes at least one comparator configured to compare a core select signal generated by the service interface with a core identifier for each of the first and second cores, and to output a comparison signal that selectively gates the service interface clock signal.

16. A circuit arrangement, comprising:

(a) a scan in port and a scan out port defining a scan path therebetween;

(b) a scan ring group disposed within the scan path between the scan in port and the scan out port, the scan ring group including an input and an output and at least a first scan ring segment with an input and an output;

(c) a second scan ring segment with an input and an output, the second scan ring segment disposed in the scan path between the scan ring group and one of the scan in and scan out ports;

(d) a first multiplexer, including first and second inputs and an output, the first and second inputs of the first multiplexer respectively coupled to the input and output of the scan ring group, and the output of the first multiplexer coupled to one of the input of the second scan ring segment and the scan out port, wherein in a first mode, the first multiplexer couples the first input to the output to bypass the scan ring group from the scan path, and in a second mode, the first multiplexer couples the second input to the output to include the scan ring group in the scan path;

(e) a third scan ring segment; and

(f) a second multiplexer coupled between the second scan ring segment and the third scan ring segment, the second multiplexer configured to selectively couple the output of the second scan ring segment to the third scan ring segment, wherein in a first mode of the second multiplexer, the third scan ring segment operates in the same scan path as the second scan ring segment, and in a second mode of the second multiplexer, the third scan ring segment operates in a separate scan path from the second scan ring segment.

17. The circuit arrangement of claim 16, wherein the first scan ring segment is the only scan ring segment in the scan ring group.

18. The circuit arrangement of claim 16, wherein the scan ring group includes at least one additional scan ring segment.

19. The circuit arrangement of claim 16, further comprising a third multiplexer including first and second inputs and an output, the first and second inputs of the third multiplexer respectively coupled to an input and an output of a second scan ring group including at least one scan ring segment, wherein in a first mode, the third multiplexer couples the first input of the third multiplexer to the output of the third multiplexer to bypass the second scan ring group from the scan path, and in a second mode, the third multiplexer couples the second input of the third multiplexer to the output of the third multiplexer to include the second scan ring group in the scan path.

20. The circuit arrangement of claim 19, wherein the second scan ring segment is disposed in the second scan ring group.

21. The circuit arrangement of claim 20, wherein the first and second scan ring groups are disposed in the same core.

22. The circuit arrangement of claim 20, wherein the first and second scan ring groups are respectively disposed in first and second cores, and wherein the first and third multiplexers are respectively responsive to first and second scan group select signals, the circuit arrangement further comprising:

(a) first and second logic gates, the first logic gate coupled between the first scan group select signal and the first multiplexer, the second logic gate coupled between the second scan group select signal and the third multiplexer; and

(b) first and second comparators respectively coupled to the first and second logic gates to selectively gate the first and second scan group select signals, the first comparator configured to receive a core select signal and a first core identifier for the first core and output therefrom a first gate signal that passes the first scan group select signal to the output of the first logic gate, and the second comparator configured to receive the core select signal and a second core identifier for the second core and output therefrom a second gate signal that passes the second scan group select signal to the output of the second logic gate.

23. The circuit arrangement of claim 19, wherein the first and second scan ring groups are respectively disposed in core scan paths in first and second cores, each core scan path including an input and an output, the circuit arrangement further comprising first and second core select circuit arrangements respectively coupled to the outputs of the core scan paths in the first and second cores, the first and second core select circuit arrangements respectively configured to couple one of the outputs of the core scan paths in the first and second cores to the scan out port in response to a core select signal.

24. The circuit arrangement of claim 23, wherein the first core select circuit arrangement includes:

(a) a comparator coupled to receive the core select signal and a core identifier for the first core and output therefrom a gate signal; and

(b) a logic gate coupled between the output of the core scan path for the first core, the logic gate configured to selectively gate the output of the core scan path for the first core in response to the gate signal from the comparator.

25. The circuit arrangement of claim 16, further comprising:

(a) a plurality of multiplexers, each configured to selectively bypass one of a plurality a scan ring groups disposed within the scan path; and

(b) a scan path register including a plurality of bits, wherein each of the plurality of bits in the scan path register is coupled to a select signal in one of the plurality of multiplexers.

26. A data processing system, comprising:

(a) a processing unit coupled to a storage unit through a bus; and

(b) an integrated circuit device disposed in one of the processing and storage units, the integrated circuit device including;

(1) first and second scan ring segments, each scan ring segment including an input and an output; and

(2) a multiplexer, coupled between the first and second scan ring segments, the multiplexer configured to selectively couple the output of the first scan ring segment to the input of the second scan ring segment, wherein in a first mode, the first and second scan ring segments operate in a common scan path, and in a second mode, the first and second scan ring segments operate in separate scan paths.

27. A data processing system, comprising:

(a) a processing unit coupled to a storage unit through a bus; and

(b) an integrated circuit device disposed in one of the processing and storage units, the integrated circuit device including;

(1) a scan in port and a scan out port defining a scan path therebetween;

(2) a scan ring group disposed within the scan path between the scan in port and the scan out port, the scan ring group including an input and an output and at least a first scan ring segment with an input and an output;

(3) a second scan ring segment with an input and an output, the second scan ring segment disposed in the scan path between the scan ring group and one of the scan in and scan out ports;

(4) a first multiplexer, including first and second inputs and an output, the first and second inputs of the first multiplexer respectively coupled to the input and output of the scan ring group, and the output of the first multiplexer coupled to one of the input of the second scan ring segment and the scan out port, wherein in a first mode, the first multiplexer couples the first input to the output to bypass the scan ring group from the scan path, and in a second mode, the first multiplexer couples the second input to the output to include the scan ring group in the scan path;

(5) a third scan ring segment; and

(6) a second multiplexer coupled between the second scan ring segment and the third scan ring segment, the second multiplexer configured to selectively couple the output of the second scan ring segment to the third scan ring segment, wherein in a first mode of the second multiplexer, the third scan ring segment operates in the same scan path as the second scan ring segment, and in a second mode of the second multiplexer, the third scan ring segment operates in a separate scan path from the second scan ring segment.

28. A program product, comprising:

(a) a hardware definition program that defines a circuit arrangement, the circuit arrangement including;

(1) first and second scan ring segments, each scan ring segment including an input and an output; and

(2) a multiplexer, coupled between the first and second scan ring segments, the multiplexer configured to selectively couple the output of the first scan ring segment to the input of the second scan ring segment, wherein in a first mode, the first and second scan ring segments operate in a common scan path, and in a second mode, the first and second scan ring segments operate in separate scan paths; and

(b) a signal bearing media bearing the hardware definition program.

29. The program product of claim 28, wherein the signal bearing media is transmission type media.

30. The program product of claim 28, wherein the signal bearing media is recordable media.

31. A program product, comprising:

(a) a hardware definition program that defines a circuit arrangement, the circuit arrangement including;

(1) a scan in port and a scan out port defining a scan path therebetween;

(2) a scan ring group disposed within the scan path between the scan in port and the scan out port, the scan ring group including an input and an output and at least a first scan ring segment with an input and an output;

(3) a second scan ring segment with an input and an output, the second scan ring segment disposed in the scan path between the scan ring group and one of the scan in and scan out ports;

(4) a first multiplexer, including first and second inputs and an output, the first and second inputs of the first multiplexer respectively coupled to the input and output of the scan ring group, and the output of the first multiplexer coupled to one of the input of the second scan ring segment and the scan out port, wherein in a first mode, the first multiplexer couples the first input to the output to bypass the scan ring group from the scan path, and in a second mode, the first multiplexer couples the second input to the output to include the scan ring group in the scan path;

(5) a third scan ring segment; and

(6) a second multiplexer coupled between the second scan ring segment and the third scan ring segment, the second multiplexer configured to selectively couple the output of the second scan ring segment to the third scan ring segment, wherein in a first mode of the second multiplexer, the third scan ring segment operates in the same scan path as the second scan ring segment, and in a second mode of the second multiplexer, the third scan ring segment operates in a separate scan path from the second scan ring segment;

(b) a signal bearing media bearing the hardware definition program.

32. The program product of claim 31, wherein the signal bearing media is transmission type media.

33. The program product of claim 31, wherein the signal bearing media is recordable media.

34. A method of interfacing with first and second scan ring segments, each of which includes an input and an output, and the first scan ring segment configured to receive a first scan in signal, the method comprising:

(a) operating the first and second scan ring segments in a common scan path by configuring a multiplexer to selectively couple the output of the first scan ring segment to the input of the second scan ring segment; and

(b) operating the first and second scan ring segments in separate scan paths by configuring the multiplexer to selectively couple the input of the second scan ring segment to receive a second scan in signal.

35. A method of interfacing with a plurality of scan ring segments disposed within a first scan path defined between a scan in port and a scan out port, each scan ring segment including an input and an output, a first scan ring segment in the plurality of scan ring segments disposed within a scan ring group including an input and an output, a second scan ring segment in the plurality of scan ring segments disposed in the first scan path between the scan ring group and one of the scan in and scan out ports, the method comprising:

(a) including the scan ring group in the first scan path by configuring a first multiplexer to couple the output of the scan ring group to one of the input of the second scan ring segment and the scan out port;

(b) bypassing the scan ring group from the first scan path by configuring the first multiplexer to couple the input of the scan ring group to the one of the input of the second scan ring segment and the scan out port;

(c) including the third scan ring segment in the first scan path by configuring a second multiplexer to selectively couple the output of the second scan ring segment to the input of the second scan ring segment; and

(d) operating the third scan ring segment in a second scan path by configuring the second multiplexer to selectively couple the input of the third scan ring segment to receive an alternate scan in signal.

36. A circuit arrangement, comprising:

(a) a scan in port and a scan out port defining a scan path therebetween;

(b) a scan ring group disposed within the scan path between the scan in port and the scan out port, the scan ring group including an input and an output and at least a first scan ring segment with an input and an output;

(c) a second scan ring segment with an input and an output, the second scan ring segment disposed in the scan path between the scan ring group and one of the scan in and scan out ports;

(d) a first multiplexer, including first and second inputs and an output, the first and second inputs of the first multiplexer respectively coupled to the input and output of the scan ring group, and the output of the first multiplexer coupled to one of the input of the second scan ring segment and the scan out port, wherein in a first mode, the first multiplexer couples the first input to the output to bypass the scan ring group from the scan path, and in a second mode, the first multiplexer couples the second input to the output to include the scan ring group in the scan path; and

(e) a second multiplexer including first and second inputs and an output, the first and second inputs of the second multiplexer respectively coupled to an input and an output of a second scan ring group including at least one scan ring segment, wherein in a first mode, the second multiplexer couples the first input of the second multiplexer to the output of the second multiplexer to bypass the second scan ring group from the scan path, and in a second mode, the second multiplexer couples the second input of the second multiplexer to the output of the second multiplexer to include the second scan ring group in the scan path.

37. A circuit arrangement, comprising:

(a) a scan in port and a scan out port defining a scan path therebetween;

(b) a scan ring group disposed within the scan path between the scan in port and the scan out port, the scan ring group including an input and an output and at least a first scan ring segment with an input and an output;

(c) a second scan ring segment with an input and an output, the second scan ring segment disposed in the scan path between the scan ring group and one of the scan in and scan out ports;

(d) a multiplexer, including first and second inputs and an output, the first and second inputs of the multiplexer respectively coupled to the input and output of the scan ring group, and the output of the multiplexer coupled to one of the input of the second scan ring segment and the scan out port, wherein in a first mode, the multiplexer couples the first input to the output to bypass the scan ring group from the scan path, and in a second mode, the multiplexer couples the second input to the output to include the scan ring group in the scan path;

(e) a plurality of multiplexers, each configured to selectively bypass one of a plurality of scan ring groups disposed within the scan path; and

(f) a scan path register including a plurality of bits, wherein each of the plurality of bits in the scan path register is coupled to a select signal in one of the plurality of multiplexers.