Structure and fabricating method of stacked capacitor

• US 6,159,793 A
• Filed: 04/26/1999
• Issued: 12/12/2000
• Est. Priority Date: 03/24/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Worldwide Semiconductor Manufacturing Corp.
• Inventors: Lou, Chine-Gie
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/299,956
• Time in Patent Office: 596 Days
• Field of Search: 438/253, 438/255, 438/256, 438/396, 438/398, 438/399, 438/665, 438/964
• US Class Current: 438/255
• CPC Class Codes: H01L 21/02263 deposition from the gas or vapour phase
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A structure and method of fabricating a stacked capacitor which forms a hemispherical grain (HSG) polysilicon on the surface of a crown shaped amorphous silicon layer. By selective tungsten deposition, the HSG polysilicon and the amorphous silicon layer are displaced with a rough tungsten layer. A material with a high dielectric constant and a metal layer are formed in sequence as a dielectric layer and an upper electrode of the capacitor, so as to form a crown metal-insulator-metal (MIM) capacitor.

Claims

1. A method of fabricating a stacked capacitor, comprising steps of:

providing a substrate;

forming a first dielectric layer on the substrate;

forming a contact in the first dielectric layer;

forming a doped polysilicon layer to fill the contact;

forming an insulating layer to cover the first dielectric layer;

forming an opening in the insulating layer to expose the contact;

forming a crown shaped amorphous silicon layer to cover the opening;

forming a plurality of hemispherical grains (HSG) polysilicon on an exposed surface of the crown shaped amorphous silicon layer;

forming a first metal layer as a lower electrode of the capacitor, the first metal layer is formed from the HSG polysilicon and the crown shaped amorphous silicon layer by a selective metal deposition;

forming a second dielectric layer to cover the first metal layer; and

forming a second metal layer to cover the second dielectric layer, wherein the second metal layer as an upper electrode of the capacitor.

2. The fabricating method of claim 1, wherein the insulating layer includes a SiN_x layer.

3. The fabricating method of claim 1, wherein the method of forming the crown shaped amorphous silicon layer, comprising steps of:

forming an amorphous silicon layer to cover the insulating layer and the opening;

forming a photoresist to cover the amorphous silicon layer;

removing the photoresist and the amorphous silicon layer that cover the surface of the insulating layer; and

removing the photoresist in the opening.

4. The fabricating method of claim 1, wherein the thickness of the crown shaped amorphous silicon layer is about 300-1000 Å

.

5. The fabricating method of claim 1, wherein the first metal layer is formed by a selective tungsten deposition.

6. The fabricating method of claim 1, wherein a pre-treatment process is performed before the first metal layer is formed.

7. The fabricating method of claim 6, wherein the solution used in the pre-treatment is a mixture of NH₄ OH and H₂ O₂.

8. The fabricating method of claim 1, wherein the second dielectric layer includes Ta₂ O₅.

9. The fabricating method of claim 1, wherein the second metal layer is formed by chemical vapor deposition (CVD) using a precursor containing TiCl₄.

10. A method of fabricating a stacked capacitor, comprising steps of:

providing a substrate;

forming a dielectric layer to cover the substrate;

forming a contact in the dielectric layer;

forming a doped polysilicon layer to fill the contact;

forming an insulating layer to cover the dielectric layer;

forming an opening in the insulating layer to expose the contact;

forming a crown shaped amorphous silicon layer to cover the opening;

forming a plurality of the HSG polysilicon on an exposed surface of the crown shaped amorphous silicon layer;

forming a tungsten layer as the lower electrode of the stacked capacitor, the tungsten layer is formed from the HSG polysilicon and the crown shaped amorphous silicon layer by a selective tungsten deposition;

forming a Ta₂ O₅ layer to cover the tungsten layer; and

forming a TiN_x layer as the upper electrode of the stacked capacitor to cover the Ta₂ O₅ layer.

11. The fabricating method of claim 10, wherein the insulating layer includes a SiN_x layer.

12. The fabricating method of claim 10, wherein the method of forming the crown shaped amorphous silicon layer comprises steps of:

forming an amorphous silicon layer to cover the insulating layer and the opening;

forming a photoresist to cover the amorphous silicon layer;

removing the photoresist and the amorphous silicon layer which cover the surface of the insulating layer;

removing the photoresist in the opening.

13. The fabricating method of claim 10, wherein the thickness of the crown shaped amorphous silicon layer is about 300-1000 Å

.

14. The fabricating method of claim 10, wherein a pre-treatment process is preformed before the first metal layer is formed.

15. The fabricating method of claim 14, wherein the solution used in the pre-treatment is a mixture of NH₄ OH and H₂ O₂.

16. The fabricating method of claim 10, wherein the TiN_x layer is formed by CVD using a precursor containing TiCl₄.