Reduced boron diffusion by use of a pre-anneal

• US 6,159,812 A
• Filed: 02/06/1998
• Issued: 12/12/2000
• Est. Priority Date: 02/06/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Wristers, Derick, Cheek, Jon, Whigham, William A.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US09/020,175
• Time in Patent Office: 1,040 Days
• Field of Search: 438/303
• US Class Current: 438/303
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method for slowing the diffusion of boron ions in a CMOS structure includes a preanneal step which can be incorporated as part of a step in which silane is deposited across the surface of the wafer. After the last implant on a CMOS device, silane (SiH₄) is deposited over the surface of the wafer using a chemical vapor deposition (CVD) tool. The deposition of silane is done at 400° C. The temperature is raised in the CVD tool to a temperature in the range of 550° C. to 650° C. and held for 30-60 minutes. This temperature does not affect the thin film of silicon which is formed from the silane, yet provides the necessary thermal cycle to "repair" the crucial first 200 Å to 600 Å of the silicon surface. Normal processing steps, including a rapid thermal anneal for 30 seconds at 1025° C. follow. The RTA is necessary to activate the dopants (arsenic and boron) in the source and drain of the respective devices. The boron dopant species diffuses less during subsequent rapid thermal anneal cycles since the crucial first 200 Å to 600 Å of the silicon surface have been repaired using this preanneal step.

Claims

1. A method for forming a MOS device, comprising:

forming a MOS structure on a substrate;

chemical-vapor depositing a substance using silane, over the MOS structure at a first selected temperature within a chamber;

raising the temperature to a second selected temperature while the MOS structure is within the chamber;

implanting a dopant and then preannealing the MOS structure by maintaining the MOS structure within the chamber at the second selected temperature for at least 30 minutes and therein repairing at least 200 Angstroms of silicon surface;

rapidly thermal annealing the MOS structure at a third temperature.

2. A method for forming a MOS device according to claim 1, wherein the first selected temperature is about 400°

C.

3. A method for forming a MOS device according to claim 1, wherein the second selected temperature is about 550-650°

C.

4. A method for forming a MOS device according to claim 1, wherein the third selected temperature is greater than 1000°

C.

5. A method for forming a MOS device according to claim 1 said at least 200 Å

of silicon surface is less than 600 Å

of silicon surface.

6. A method for forming a MOS device according to claim 2, wherein the first selected temperature is about 400°

C. and the second selected temperature is about 550-650°

C.

7. A method for forming a MOS device according to claim 6, wherein the third selected temperature is greater than 1000°

C.

8. A method for forming a MOS device according to claim 7, wherein said at least 200 Å

of silicon surface is less than 600 Å

of silicon surface.

9. A method for forming a MOS device according to claim 8, further including implanting a dopant before the preannealing.

11. The method of claim 1, wherein the step of heating the substrate to a selected temperature and holding the temperature for a selected time is completed while the substrate is held in a device associated with another process step.

10. A method for forming a MOS device, comprising:

forming a MOS structure on a substrate;

chemical-vapor depositing a thin film, using silane, over the MOS structure at a first selected temperature within a chamber;

raising the temperature to a second selected temperature while the MOS structure is within the chamber;

implanting a boron dopant;

preannealing the MOS structure by maintaining the MOS structure within the chamber at the second selected temperature for at least 30 minutes and therein repairing at least 200 Angstroms of silicon surface; and

rapidly thermal annealing the MOS structure at a third temperature.