Methods for shallow trench isolation

• US 6,159,821 A
• Filed: 02/12/1999
• Issued: 12/12/2000
• Est. Priority Date: 02/12/1999
• Status: Expired due to Term

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Yang, Fu-Liang, Cheng, Hsu-Li, Lin, Wei-Ray
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Blum, David S
• Application Number:
  US09/249,255
• Time in Patent Office: 669 Days
• Field of Search: 438/424, 438/221, 438/296, 438/359, 438/427
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material

Abstract

A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide layers into the semiconductor substrate. A layer of oxide is then deposited over the said nitride layer and within the isolation trenches. The oxide layer is then polished away through chemical and mechanical polishing wherein the substrate is planarized. The nitride layer is then etched away using a special dry-etch recipe that has a higher etching rate for silicon nitride than oxide. The dry-etch recipe also has a very low etching rate for the silicon substrate. This results in the removal of the nitride layer, rounding the shoulders of the trench and leaving the substrate unaffected. The fabrication of the integrated circuit device is completed.

Claims

1. A method of manufacturing an integrated circuit device comprising:

providing a pad oxide layer over the surface of a silicon semiconductor substrate;

depositing a sacrificial oxide layer overlying said pad oxide layer;

depositing a nitride layer overlying said sacrificial oxide layer;

etching a plurality of isolation trenches through said nitride, sacrificial oxide, and said pad oxide layers into said semiconductor substrate;

depositing an oxide layer over said nitride layer and within said isolation trenches;

polishing away said oxide layer wherein said substrate is planarized;

etching back said nitride and oxide layers using an etching recipe that has a lower etching rate for said silicon substrate as compared with the etching rate of said nitride and oxide layers, and has a higher etching rate for the said nitride layer as compared with the said oxide layer whereby said nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and whereby the corners of said trench isolation areas are rounded; and

completing the fabrication of said integrated circuit device.

2. The method according to claim 1 wherein said silicon nitride layer has a thickness of between about 1500 and 3000 Angstroms.

3. The method according to claim 1 wherein said oxide layer has a thickness of between about 5000 and 8000 Angstroms.

4. The method according to claim 1 wherein said polishing is done by chemical mechanical polishing.

5. The method according to claim 1 wherein said etching back is performed with a selectivity of silicon nitride to oxide of (1.1-1.5) to 1.0.

6. The method according to claim 1 wherein said etching back is performed with a selectivity of silicon nitride to said silicon semiconductor substrate of greater than 5.

7. The method according to claim 1 wherein said etching back is performed using a dry-etch recipe with the following parameters:

O₂ flow;

between about 2 sccm and 10 sccm,

CHF₃ flow;

between about 5 sccm and 30 sccm,

CF₄ flow;

between about 5 sccm and 30 sccm,

pressure;

between about 10 m Torr and 200 m Torr, and

rf-power;

between about 300 Watts and 800 Watts.

8. The method according to claim 1 wherein said completing fabrication of said integrated circuit comprises fabricating semiconductor device structures in and on said semiconductor substrate between and over said isolation trenches.

9. A method of manufacturing an integrated circuit device comprising:

providing a pad oxide layer over the surface of a silicon semiconductor substrate;

depositing a sacrificial oxide layer overlying said pad oxide layer;

depositing a nitride layer overlying said sacrificial oxide layer;

etching a plurality of isolation trenches through said nitride layer, said sacrificial oxide layer and said pad oxide layer into said silicon semiconductor substrate;

depositing an oxide layer over said nitride layer and within said isolation trenches;

polishing away said oxide layer wherein said substrate is planarized;

etching back said nitride layer with a recipe having a selectivity of nitride to silicon of greater than 5 and a selectivity of nitride to oxide of (1.1-1.5) to 1.0 whereby said nitride layer is etched away and said sacrificial oxide layer and sharp corners of said trench isolation areas are etched away; and

completing the fabrication of said integrated circuit device.

10. The method according to claim 9 wherein said sacrificial oxide layer has a thickness of between about 150 and 500 Angstroms.

11. The method according to claim 9 wherein said oxide layer has a thickness of between about 2500 and 5000 Angstroms.

12. The method according to claim 9 wherein said polishing is done by chemical mechanical polishing.

13. The method according to claim 9 wherein said etching back is performed using a dry-etch recipe with the following parameters:

O₂ flow;

between about 2 sccm and 10 sccm,

CHF₃ flow;

between about 5 sccm and 30 sccm,

CF₄ flow;

between about 5 sccm and 30 sccm,

pressure;

between about 10 m Torr and 200 m Torr, and

rf-power;

between about 300 Watts and 800 Watts.

14. The method according to claim 9 wherein said completing fabrication of said integrated circuit comprises fabricating semiconductor device structures in and on said semiconductor substrate between and over said isolation trenches.

15. A method of manufacturing an integrated circuit device comprising:

providing a pad oxide layer over the surface of a silicon semiconductor substrate;

depositing a sacrificial oxide layer overlying said pad oxide layer;

depositing a silicon nitride layer overlying said sacrificial oxide layer;

etching a plurality of isolation trenches through said silicon nitride layer, said sacrificial oxide layer, and said pad oxide layer into said semiconductor substrate;

depositing an oxide layer over said silicon nitride layer and within said isolation trenches;

polishing away said oxide layer wherein said substrate is planarized;

etching back said silicon nitride layer using a dry etch recipe comprising O₂, CHF₃, and CF₄ and having a selectivity of silicon nitride to silicon of greater than 5 and a selectivity of silicon nitride to oxide of (1.1-1.5) to 1.0 whereby said silicon nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and sharp corners of said trench isolation areas are etched away; and

completing the fabrication of said integrated circuit device.

16. The method according to claim 15 wherein said sacrificial oxide layer has a thickness of between about 150 and 500 Angstroms.

17. The method according to claim 15 wherein said oxide layer has a thickness of between about 2500 and 5000 Angstroms.

18. The method according to claim 15 wherein said polishing is done by chemical mechanical polishing.

19. The method according to claim 15 wherein said etching back is performed using a dry-etch recipe with the following parameters:

O₂ flow;

between about 2 sccm and 10 sccm,

CHF₃ flow;

between about 5 sccm and 30 sccm,

CF₄ flow;

between about 5 sccm and 30 sccm,

pressure;

between about 10 m Torr and 200 m Torr, and

rf-power;

between about 300 Watts and 800 Watts.