Methods for shallow trench isolation
First Claim
1. A method of manufacturing an integrated circuit device comprising:
- providing a pad oxide layer over the surface of a silicon semiconductor substrate;
depositing a sacrificial oxide layer overlying said pad oxide layer;
depositing a nitride layer overlying said sacrificial oxide layer;
etching a plurality of isolation trenches through said nitride, sacrificial oxide, and said pad oxide layers into said semiconductor substrate;
depositing an oxide layer over said nitride layer and within said isolation trenches;
polishing away said oxide layer wherein said substrate is planarized;
etching back said nitride and oxide layers using an etching recipe that has a lower etching rate for said silicon substrate as compared with the etching rate of said nitride and oxide layers, and has a higher etching rate for the said nitride layer as compared with the said oxide layer whereby said nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and whereby the corners of said trench isolation areas are rounded; and
completing the fabrication of said integrated circuit device.
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Abstract
A method for forming self-rounded shallow trench isolation is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is then deposited overlying the pad oxide layer. Isolation trenches are then etched through the nitride and pad oxide layers into the semiconductor substrate. A layer of oxide is then deposited over the said nitride layer and within the isolation trenches. The oxide layer is then polished away through chemical and mechanical polishing wherein the substrate is planarized. The nitride layer is then etched away using a special dry-etch recipe that has a higher etching rate for silicon nitride than oxide. The dry-etch recipe also has a very low etching rate for the silicon substrate. This results in the removal of the nitride layer, rounding the shoulders of the trench and leaving the substrate unaffected. The fabrication of the integrated circuit device is completed.
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Citations
19 Claims
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1. A method of manufacturing an integrated circuit device comprising:
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providing a pad oxide layer over the surface of a silicon semiconductor substrate; depositing a sacrificial oxide layer overlying said pad oxide layer; depositing a nitride layer overlying said sacrificial oxide layer; etching a plurality of isolation trenches through said nitride, sacrificial oxide, and said pad oxide layers into said semiconductor substrate; depositing an oxide layer over said nitride layer and within said isolation trenches; polishing away said oxide layer wherein said substrate is planarized; etching back said nitride and oxide layers using an etching recipe that has a lower etching rate for said silicon substrate as compared with the etching rate of said nitride and oxide layers, and has a higher etching rate for the said nitride layer as compared with the said oxide layer whereby said nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and whereby the corners of said trench isolation areas are rounded; and completing the fabrication of said integrated circuit device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of manufacturing an integrated circuit device comprising:
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providing a pad oxide layer over the surface of a silicon semiconductor substrate; depositing a sacrificial oxide layer overlying said pad oxide layer; depositing a nitride layer overlying said sacrificial oxide layer; etching a plurality of isolation trenches through said nitride layer, said sacrificial oxide layer and said pad oxide layer into said silicon semiconductor substrate; depositing an oxide layer over said nitride layer and within said isolation trenches; polishing away said oxide layer wherein said substrate is planarized; etching back said nitride layer with a recipe having a selectivity of nitride to silicon of greater than 5 and a selectivity of nitride to oxide of (1.1-1.5) to 1.0 whereby said nitride layer is etched away and said sacrificial oxide layer and sharp corners of said trench isolation areas are etched away; and completing the fabrication of said integrated circuit device. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method of manufacturing an integrated circuit device comprising:
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providing a pad oxide layer over the surface of a silicon semiconductor substrate; depositing a sacrificial oxide layer overlying said pad oxide layer; depositing a silicon nitride layer overlying said sacrificial oxide layer; etching a plurality of isolation trenches through said silicon nitride layer, said sacrificial oxide layer, and said pad oxide layer into said semiconductor substrate; depositing an oxide layer over said silicon nitride layer and within said isolation trenches; polishing away said oxide layer wherein said substrate is planarized; etching back said silicon nitride layer using a dry etch recipe comprising O2, CHF3, and CF4 and having a selectivity of silicon nitride to silicon of greater than 5 and a selectivity of silicon nitride to oxide of (1.1-1.5) to 1.0 whereby said silicon nitride layer is etched away, said sacrificial oxide layer is etched away whereby said pad oxide layer is left overlying and protecting said silicon semiconductor substrate, and sharp corners of said trench isolation areas are etched away; and completing the fabrication of said integrated circuit device. - View Dependent Claims (16, 17, 18, 19)
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Specification