Silicon-on-silicon wafer bonding process using a thin film blister-separation method

• US 6,159,824 A
• Filed: 02/19/1998
• Issued: 12/12/2000
• Est. Priority Date: 05/12/1997
• Status: Expired due to Term

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J., Cheung, Nathan W.
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): Chen, Kin-Chan
• Application Number:
  US09/025,967
• Time in Patent Office: 1,027 Days
• Field of Search: 438/690, 438/455, 438/691, 438/692, 438/798, 438/706, 438/977
• US Class Current: 438/455
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 2201/0192 by cleaving the carrier wafer
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: Y10S 117/915 Separating from substrate
• CPC Class Codes: Y10S 156/93 Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 156/11 Methods of delaminating, per se; i.e. , separating at bonding face
• CPC Class Codes: Y10T 156/1158 Electromagnetic radiation applied to work for delamination [e.g., microwave, uv, ir, etc.]
• CPC Class Codes: Y10T 156/19 Delaminating means
• CPC Class Codes: Y10T 428/21 Circular sheet or circular blank
• CPC Class Codes: Y10T 428/24893 : including particulate material
• CPC Class Codes: Y10T 428/249956 : Void-containing component is inorganic

Abstract

A method for fabricating silicon-on-silicon substrates. A donor wafer (40) is attached to a target wafer (46) using a low-temperature bonding process. The low-temperature bonding process maintains the integrity of a layer of microbubbles (41). Subsequent processing separates a thin film (45) of material from the donor wafer. A high-temperature annealing process finishes the bonding process of the thin film to the target wafer to produce a hybrid wafer suitable for fabricating integrated circuit devices or other devices.

Claims

1. The process for fabricating a silicon-on-silicon wafer, said process comprising steps of:

providing one of a {100}, a {110}, or a {111} crystallographic plane single-crystal silicon donor wafer with a first polished surface;

implanting hydrogen or helium ions through said first polished surface to a first depth to form a layer of microbubbles;

bonding the first polished surface of the donor wafer to a second polished surface of a single-crystal silicon target wafer at a bonding temperature less than about 500°

C., including activating the first and second polished surfaces by plasma cleaning and bringing the first and second surfaces into contact with each other to form an intermediate wafer assembly;

heating the intermediate wafer assembly to separate a thin film of material from the donor wafer, the thin film adhering to the target wafer to form a hybrid substrate assembly; and

annealing the hybrid substrate assembly to strengthen the bond between the thin film and the target wafer and to create electrical contact between the thin film and the target wafer.

2. The process of claim 1 wherein the plasma cleaning includes producing a plasma with a gas selected from the group consisting of argon, ammonia, neon, water vapor and oxygen.

3. The process of claim 1 wherein the step of annealing the hybrid substrate assembly is a continuation of the step of heating the intermediate wafer assembly.

4. The process of claim 1 further comprising a step, after the step of heating the intermediate wafer assembly, of polishing a separated surface of the hybrid substrate assembly.

5. The process of claim 1 wherein said {100} crystallographic plane is parallel to said first polished surface.

6. The process of claim 1 wherein said {110} crystallographic plane is substantially parallel to said first polished surface.

7. The process of claim 1 wherein said {111} crystallographic plane substantially parallel to said first polished surface.

8. The process of claim 7 wherein said {111} crystallographic plane is about three degrees from said first polished surface.