Method for reducing resistance of contact window

• US 6,159,850 A
• Filed: 08/07/1998
• Issued: 12/12/2000
• Est. Priority Date: 06/16/1998
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Kuo, Chien-Li, Lee, Tzung-Han
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/130,944
• Time in Patent Office: 858 Days
• Field of Search: 438/665, 438/637
• US Class Current: 438/665
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method of reducing resistance of a contact. A semiconductor substrate having at least a conductive lines formed thereon is provided. A self-aligned contact window is formed to expose a part of the substrate. A recess with a ragged surface is formed on the exposed part of substrate within the contact window.

Claims

1. A method of forming an electrically enhanced contact surface in a self-aligned contact window comprising the steps of:

providing a substrate having a plurality of gates, wherein each gate has a spacer on each side wall of the gate and a cap layer on the gate;

forming an oxide layer over the gates and the substrate;

forming a photo-resist layer with an opening on the oxide layer, wherein the opening exposes a part of the oxide layer aligned with a predetermined source/drain region of the substrate between the gates;

etching the oxide layer using the photo-resist layer, the spacer and the cap layer as a mask to form the contact window to expose the predetermined source/drain region;

etching the predetermined source/drain region by a soft-etching process and forming a recess with a rough surface within the contact window; and

performing an ion implantation to form a charge barrier underlying a top surface of the predetermined source/drain region to prevent charge leakage due to the rough surface of the recess.

2. The method according to claim 1, wherein the recess is formed with a depth between 100 Å

to 300 Å

.

3. The method according to claim 1, wherein the ions used in the ion implantation for forming the charge barrier are P-type ions.

4. The method according to claim 1, wherein the ions used in the ion implantation for forming the charge barrier are N-type ions.

5. The method according to claim 1, wherein the spacer is formed by silicon nitride.

6. The method according to claim 1, wherein the cap layer is formed by silicon nitride.

7. The method according to claim 1, wherein the etching of the oxide layer is a high selective anisotropic etching.

18. The method according to claim 1, wherein the charge barrier is substantially not formed under the gates.

20. The method according to claim 1, wherein the soft-etching process is an isotropic etching with a zero bias.

8. A method of forming an electrically enhanced contact surface in a self-aligned contact window comprising the steps of:

providing a substrate on which at least a pair of gates is formed with a spacer on each side wall of the gate, a cap layer on the gate and an oxide layer over the gate and the substrate;

patterning the oxide layer to form a contact window to expose the substrate between the gates;

etching the substrate by a soft-etching process and forming a recess with a rough surface within the contact window; and

performing an ion implantation to form a charge barrier underlying the rough surface of the recess to prevent charge leakage due to the rough surface.

9. The method according to claim 8, wherein the exposed substrate within the contact window comprises a predetermined source/drain region.

10. The method according to claim 8, wherein the etching of the oxide layer is a high selective anisotropic etching.

11. The method according to claim 8, wherein the soft-etching process is an isotropic etching with a reduced bias.

12. The method according to claim 8, wherein the soft-etching process is an isotropic etching with a zero bias.

13. The method according to claim 8, wherein the recess is formed with a depth between 100 Å

to 300 Å

.

14. The method according to claim 8, wherein the ions used in the ion implantation for forming the charge barrier are P-type ions.

15. The method according to claim 8, wherein the ions used in the ion implantation for forming the charge barrier are N-type ions.

16. The method according to claim 8, wherein the spacer is formed by silicon nitride.

17. The method according to claim 8, wherein the cap layer is formed by silicon nitride.

19. The method according to claim 8, wherein the charge barrier is substantially not formed under the gates.