Field effect transistor

• US 6,160,280 A
• Filed: 03/04/1996
• Issued: 12/12/2000
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Norris, George B., Golio, John Michael, Bonn, Fred H.
• Primary Examiner(s): Loke, Steven H.
• Assistant Examiner(s): Tran, Thien F.
• Application Number:
  US08/610,504
• Time in Patent Office: 1,744 Days
• Field of Search: 455/333, 455/323, 455/325, 455/326, 455/319, 455/209, 455/318, 455/311, 455/313, 455/330, 327/408, 327/404, 327/416, 327/356, 327/113, 257/368, 257/365, 257/369, 257/256, 257/270, 257/272, 257/280, 257/281, 257/285, 257/286, 257/287, 257/404, 257/194, 257/192
• US Class Current: 257/272
• CPC Class Codes: H01L 29/8124 with multiple gate
• CPC Class Codes: H03D 7/125 with field effect transistors

Abstract

A field effect transistor structure which can serve as a low noise amplifier. The field effect transistor has a major surface and source and drain regions extending from the major surface into a body of semiconductor material. A channel region is formed in a portion of the body of semiconductor material separating the source and drain regions. The channel region has a first boundary perpendicular to the major and contiguous with the source region, a second boundary parallel to the first boundary and contiguous with the drain region, a third boundary perpendicular to the first boundary, and a fourth boundary parallel to the channel region. A first portion of the channel region is enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, a third boundary of the channel region, and the fourth boundary of the channel region. A non-conductive section is formed in the body of semiconductor material extending from the major surface and enclosed by a first edge coinciding with the first border of the first portion of the channel region, a second edged coinciding with the second border of the first portion of the channel region, a third edge parallel to the third boundary of the channel region, and a fourth edge parallel to the fourth boundary of the channel region. A gate structure is formed above the first portion of the channel region.

Claims

1. A field effect transistor structure, comprising:

a body of semiconductor material having a major surface;

a source region formed in the body of semiconductor material extending from the major surface;

a drain region formed in the body of semiconductor material extending from the major surface;

a channel region having a first type of conductivity formed in the body of semiconductor material separating the source region from the drain region, wherein the channel region has a first boundary perpendicular to the major surface and contiguous with the source region, a second boundary parallel to the first boundary and contiguous with the drain region, a third boundary perpendicular to the major surface and perpendicular to the first boundary, and a fourth boundary parallel to the third boundary;

a first portion of the channel region enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, the third boundary of the channel region, and the fourth boundary of the channel region;

a second portion of the channel region enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, the third boundary of the channel region, and the fourth boundary of the channel region;

a non-conductive section formed in the body of semiconductor material extending from the major surface and enclosed by a first edge coinciding with the first border of the first portion of the channel region, a second edge coinciding with the second border of the first portion of the channel region, a third edge parallel to the third boundary of the channel region, and a fourth edge parallel to the fourth boundary of the channel region, wherein the third and fourth edges are located between the third and fourth boundaries of the channel region;

a first gate structure formed on the major surface above the first portion of the channel region; and

a second gate structure formed on the major surface above the second portion of the channel region.

2. The field effect transistor structure of claim 1, wherein the second portion of the channel region is between the first portion of the channel region and the drain region.

3. The field effect transistor structure of claim 1, wherein the first portion of the channel region has a first dopant concentration and the second portion of the channel region has a second dopant concentration, and wherein the first dopant concentration is different from the second dopant concentration.

4. The field effect transistor structure of claim 1, wherein the first portion of the channel region extends from the major surface to a first channel depth and the second portion of the channel region extends from the major surface to a second channel depth, and wherein the first channel depth is different from the second channel depth.

5. A multi-gate field effect transistor structure, comprising:

a body of semiconductor material having a major surface;

a source region formed in the body of semiconductor material extending from the major surface;

a drain region formed in the body of semiconductor material extending from the major surface;

a channel region having a first type of conductivity formed in the body of semiconductor material separating the source region from the drain region, wherein the channel region has a first boundary perpendicular to the major surface and contiguous with the source region, a second boundary parallel to the first boundary and contiguous with the drain region, a third boundary perpendicular to the major surface and perpendicular to the first boundary, and a fourth boundary parallel to the third boundary;

a first gate region having a first dopant concentration and the first type of conductivity formed in the channel region extending from the major surface, wherein the first gate region is enclosed by a first border parallel to the first boundary of the channel region, a second border parallel to the second boundary of the channel region, the third boundary of the channel region, and the fourth boundary of the channel region;

a first gate formed on the major surface above the first gate region;

a second gate region having a second dopant concentration and the first type of conductivity formed in the channel region, outside the first gate region, and extending from the major surface; and

a second gate formed on the major surface above the second gate region.

6. The multi-gate field effect transistor structure of claim 5, further comprising a plurality of non-conductive sections formed in the first gate region, each non-conductive section of the plurality of non-conductive sections enclosed by a first edge coinciding with the first border of the first gate region, a second edge coinciding with the second border of the first gate region, a third edge parallel to the third boundary of the channel region, and a fourth edge parallel to the fourth boundary of the channel region.

7. The multi-gate field effect transistor structure of claim 5, wherein the second gate region is between the first gate region and the drain region.

8. The multi-gate field effect transistor structure of claim 5, wherein the first gate region extends from the major surface to a first channel depth and the second gate region extends from the major surface to a second channel depth, and wherein the first channel depth is different from the second channel depth.

9. A multi-fingered field effect transistor structure, comprising:

a body of semiconductor material having a major surface;

a plurality of source regions formed in the body of semiconductor material extending from the major surface, wherein the plurality of source regions are commonly coupled to a source probe pad;

a plurality of drain regions formed in the body of semiconductor material extending from the major surface, wherein the plurality of drain regions are commonly coupled to a drain probe pad;

a plurality of channel regions having a first type of conductivity formed in the body of semiconductor material separating the plurality of source regions from the plurality of drain regions, wherein a channel region of the plurality of channel regions has a first boundary perpendicular to the major surface and contiguous with a corresponding source region of the plurality of source regions, a second boundary parallel to the first boundary and contiguous with a corresponding drain region the plurality of drain regions, a third boundary perpendicular to the major surface and perpendicular to the first boundary, and a fourth boundary parallel to the third boundary;

a plurality of first gate regions having the first type of conductivity formed in the plurality of channel regions extending from the major surface to a first channel depth, wherein each first gate region of the plurality of first gate regions is enclosed by a first border parallel to the first boundary of a corresponding channel region of the plurality of channel regions, a second border parallel to the second boundary of the corresponding channel region, the third boundary of the corresponding channel region, and the fourth boundary of the corresponding channel region;

a plurality of second gate regions having the first type of conductivity formed in the plurality of channel regions, outside the plurality of first gate regions, and extending from the major surface to a second channel depth;

a plurality of first gates formed on the major surface above the plurality of first gate regions, wherein the plurality of first gates are commonly coupled to a first gate probe pad; and

a plurality of second gates formed on the major surface above the plurality of second gate regions, wherein the plurality of second gates are commonly coupled to a second gate probe pad.

10. The multi-fingered field effect transistor structure of claim 9, further comprising a plurality of non-conductive sections formed in the plurality of first gate regions and extending from the major surface to the first channel depth, each non-conductive section of the plurality of non-conductive sections enclosed by a first edge coinciding with the first border of a corresponding first gate region of the plurality of first gate regions, a second edge coinciding with the second border of the corresponding first gate region, a third edge parallel to the third boundary of a corresponding channel region of the plurality of channel regions, and a fourth edge parallel to the fourth boundary of the corresponding channel region.

11. The multi-fingered field effect transistor structure of claim 9, wherein each second gate region of the plurality of second gate regions is between a corresponding first gate region of the plurality of first gate regions and a corresponding drain region of the plurality of drain regions.

12. The multi-fingered field effect transistor structure of claim 9, wherein the plurality of first gate regions have a first dopant concentration and the plurality of second gate regions have a second dopant concentration, and wherein the first dopant concentration is different from the second dopant concentration.