Circuit and methods to improve the operation of SOI devices

• US 6,160,292 A
• Filed: 04/22/1998
• Issued: 12/12/2000
• Est. Priority Date: 04/23/1997
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Hsu, Louis L., Kuang, Jente B., Flaker, deceased, Roy Childs
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Fenty, Jesse A
• Application Number:
  US09/063,823
• Time in Patent Office: 965 Days
• Field of Search: 257/355, 257/347, 257/349, 257/350, 257/351, 257/352
• US Class Current: 257/347
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable Vt effect is preserved. The overall body resistance of the individual devices has a minimal effect on the device body potential.

Claims

1. In a circuit comprising a plurality of SOI devices wherein each of the SOI devices has a body, a mechanism for enhancing the performance of the circuit, the mechanism comprising:

a circuit component comprising a pulse discharge circuit for discharging accumulated electrical potential from the body of the plurality of SOI devices by applying a pulse at source functions of the SOI devices.

2. The mechanism of claim 1 wherein the circuit component comprises a connection to ground for at least one of the bodies of the SOI devices.

3. The mechanism of claim 1 wherein the pulse discharge circuit comprises:

an input signal;

a delay element coupled to the input signal; and

an output signal coupled to the input signal, the output signal driving the circuit.

4. The mechanism of claim 1 wherein the pulse discharge circuit further comprises a pulse generator.