Programmable interconnect architecture

• US 6,160,420 A
• Filed: 11/12/1996
• Issued: 12/12/2000
• Est. Priority Date: 09/19/1986
• Status: Expired due to Fees

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Gamal, Abbas El, El-Avat, Khaled A., Mohsen, Amr
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US08/754,189
• Time in Patent Office: 1,491 Days
• Field of Search: 326/38-41, 326/44, 326/49, 327/525
• US Class Current: 326/41
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318519 Test of field programmable gate arrays [FPGA]
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Claims

1. A logic function circuit interconnect architecture for a user-programmable integrated circuit disposed on a substrate, said integrated circuit comprising:

a plurality of logic function circuits placed in an array on said substrate;

said array arranged as a plurality of rows and columns of said logic function circuits, each of said logic function circuits having a discernable height and width, and including at least one input and at least one output;

said interconnect architecture including a plurality of sets of interconnect busses, each of said rows of said logic function circuits associated with at least one of said sets of interconnect busses and each of said columns of said logic function circuits associated with at least one other of said sets of interconnect busses;

said sets of interconnect busses comprising wiring channels, at least one of said outputs of said logic function circuits being user-connectable through a single user-programmable element to at least one of said wiring channels of at least two of said sets of interconnect busses;

said sets of interconnect busses associated with said columns of said logic function circuits cross said sets of interconnect busses associated with said rows of said logic function circuits at intersections;

a plurality of said wire channels of said sets of interconnect busses associated with said columns of said logic function circuits are user-interconnectable at said intersections to a plurality of said wiring channels of said sets of said interconnect busses associated with said rows of said logic function circuits;

said wiring channels comprise user-interconnectable segments of minimum fixed lengths spanning rows and columns of said logic function circuits of said array; and

said wire segments of said interconnect busses are electrically user-interconnectable to an adjacent one of said wire segments in said same wiring channel and wherein said wire segments are offset.

2. The logic function circuit interconnect architecture of claim 1 wherein said logic function circuits comprise at least one RAM element.

3. The logic function circuit interconnect architecture according to claim 2 further comprising:

series-pass transistors, having control elements, connecting selected adjacent and intersecting ones of said segments; and

selection circuitry connected to the control element of each of series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

4. An electrically programmable interconnect architecture, comprising:

a plurality of modules placed in an array, the modules having connection nodes;

a plurality of sets of wiring channels, at least some of said sets of wiring channels having at least one wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments in connected to at least one of said connection nodes;

a plurality of two terminal, normally-open, electrically-programmable elements, each of said elements located between selected ones of said wiring segments comprising one of said channels, said programmable elements being characterized by a high impedance before programming and being selectably programmable by the user in order to create a permanent bi-directional low impedance electrical connection between wire segments.

5. The electrically-programmable interconnect architecture of claim 4 wherein at least one of said wiring channels lies in a direction substantially non-parallel to the remainder of said wiring channels and is disposed in a layer electrically isolated from the layer containing said remainder of wiring channels, forming intersections.

6. The electrically-programmable interconnect architecture according to claim 5 further comprising:

series-pass transistors, having control elements, connecting selected adjacent and intersecting ones of said segments; and

selection circuitry connected to the control element of each of series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

7. The electrically-programmable interconnect architecture of claim 4, further comprising:

programming elements joining selected ones of those wiring segments of said sets of wiring channels which interest each other at said intersections.

8. The electrically-programmable interconnect architecture according to claim 4 further comprising:

series-pass transistors, having control elements, connecting selected adjacent and intersecting ones of said segments; and

selection circuitry connected to the control element of each of series-pass transistors capable of selectively biasing each one of said series-pass transistors to cause it to conduct or not to conduct.

9. An electrically programmable interconnect architecture, comprising:

a plurality of modules placed in an array, the modules having connection nodes;

a plurality of sets of wiring channels, each set of wiring channels having at least wiring channel comprising at least two wiring segments and wherein at least one of said wiring segments is connected to one of said connection nodes;

a plurality of normally-open, electrically-programmable elements, each of said elements located between selected ones of said wiring segments, said programmable elements being characterized by a high impedance before programming and being selectively programmable by the user in order to create a bi-directional low-impedance electrically connection between wiring segments;

series-pass transistors connected between selected ones of said wiring segments, each of said series-pass transistors having a control element; and

selection circuitry connected to said control elements of each of said series-pass transistors.

10. The electrically-programmable interconnect architecture of claim 9, further including:

means for selectively applying a programming voltage to selected ones of said wiring segments.

11. An electrically-programmable interconnect architecture, comprising:

a plurality of function modules, having connection nodes;

a plurality of wiring channels, selected ones of said wiring channels being arranged has at least two wiring segments, at least one of said writing segments being connected to one of said connection nodes;

a plurality of electrically-programmable elements, connected between selected ones of said wiring segments;

series-pass means, connected in parallel with selected ones of said electrically-programmable elements, for temporarily causing electrical connections between said wiring segments to which they are connected; and

selection means for providing signals to said series-pass means, to cause said series-pass means to temporarily conduct.