Driver with switchable gain

• US 6,160,436 A
• Filed: 03/31/1999
• Issued: 12/12/2000
• Est. Priority Date: 04/17/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Runaldue, Thomas J.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/281,905
• Time in Patent Office: 622 Days
• Field of Search: 327/543, 327/407-413, 327/538, 327/403-404, 323/315, 330/288
• US Class Current: 327/407
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 41/046 comprising network management agents or mobile agents therefor
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]

Abstract

A driver having a switchable gain including a first circuit connected to a potential source, an input node receiving an input current, and an output node and operable in both low and high transmission frequency modes, and a second circuit connected to the potential source and a node of the first circuit and operable in only the high transmission frequency mode. In the low transmission frequency mode, the potential source is at a first level and the first circuit receives the input current and provides a first output current with a first current gain to the output node. In the high transmission frequency mode, the potential source is at a second, lower level and the first and second circuits receive the input current and provide a second output current, less than the first output current, with a second current gain, lower than the first current gain, to the output node.

Claims

1. A transmission line driver operable in low and high frequency transmission modes, comprising:

low transmission frequency mode circuitry that receives a first input current and generates a first output current with a first current gain;

high transmission frequency mode circuitry that receives a second input current, different from the first input current, and generates a second output current that is less than the first output current and with a second current gain that is less than the first current gain;

wherein

the transmission line driver is responsive to a control signal designating the low transmission frequency mode to cause the low transmission frequency mode circuitry to generate the first output current and to the control signal designating the high transmission frequency mode to cause the high transmission frequency mode circuitry to generate the second output current.

2. The driver according to claim 1, wherein the low frequency mode circuitry comprises a current mirror.

3. The driver according to claim 2, wherein the current mirror includes a first transistor and a second transistor, the first transistor having a source coupled to a voltage source, and a drain and a gate coupled to a conductor receiving the first current during the low frequency mode and the second current during the high frequency mode, the second transistor having a source coupled to the voltage source, a gate coupled to the conductor connected to the drain and gate of the first transistor, and a drain at which the first and second output currents are generated.

4. The driver according to claim 3, wherein the high frequency mode circuitry comprises the current mirror and a third transistor that is connected in parallel to the first transistor, with a source coupled to the voltage source, a drain coupled to the conductor connected to the drain and gate of the first transistor, and a gate that is controllably coupled to the conductor connected to the drain and gate of the first transistor.

5. The driver according to claim 4, further comprising control circuitry coupled to the gate of the third transistor to control the operation of the third transistor such that the gate of the third transistor is coupled to the conductor connected to the drain and gate of the first transistor only during the high frequency mode.

6. The driver according to claim 5, wherein the control circuitry comprises a fourth transistor coupled between the voltage source and the gate of the third transistor and having a gate receiving the control signal designating the low or high frequency mode, a fifth transistor connected between the gate of the third transistor and to the drain and gate of the first transistor, an inverter having an input receiving the control signal and an output connected to the gate of the fifth transistor.

7. The driver according to claim 6, wherein

in the low frequency mode, the fourth transistor is ON and the third and fifth transistors are OFF, and

in the high frequency mode, the fourth transistor is OFF and the third and fifth transistors are ON.

8. A transmission line driver operable in a low transmission frequency mode and a high transmission frequency mode, comprising:

a first circuit operable in both the low and high transmission frequency modes and connected to (i) a potential source, (ii) an input node receiving an input current, and (iii) an output node providing an output current, and

a second circuit operable in only the high transmission frequency mode and connected to the potential source and controllably connected to the input node.

9. The driver according to claim 8, wherein

the first circuit is a current mirror having a first transistor and a second transistor, said first transistor having a first conductor connected to said potential source, a second conductor connected to said input node and a gate connected to said input node, and said second transistor having a first conductor connected to said potential source, a second conductor connected to said output node and a gate connected to said input node.

10. The driver according to claim 9, wherein

the second circuit comprises a third transistor having a first conductor connected to said potential source, a second conductor connected to the input node, and a gate controllably connected to the input node,

in said low transmission frequency mode

said potential source is at a first level,

a first input current is provided to said input node, and

said first circuit provides a first output current with a first current gain to said output node, and

in said high frequency mode,

said potential source is at a second lower level,

a second lower input current is provided to said input node, and

said first and second circuits provide a second output current less than the first output current, with a second current gain lower than the first current gain, to said output node.

11. The driver according to claim 10, wherein

the second circuit further comprises

an inverter receiving a transmission frequency mode selection signal and outputting an inverted transmission frequency mode selection signal,

a fourth transistor having a first conductor connected to the potential source, a second conductor connected to the gate of the third transistor and a gate receiving the transmission frequency mode selection signal, and

a fifth transistor having a first conductor connected to the input node, a second conductor connected to the gate of the third transistor and the second conductor of the fourth transistor, and a gate receiving the inverted transmission frequency mode selection signal.

12. The driver according to claim 11, wherein the first through fifth MOS transistors are all the same type MOS transistor.

13. The driver according to claim 8, wherein the low transmission frequency mode is 10 Mb/s and the high transmission frequency mode is 100 Mb/s.

14. The driver according to claim 13, wherein in the low transmission frequency mode the driver has to drive about 1.8 to 2.5 volts, and in the high transmission frequency mode, the driver has to drive about 1 volt.

15. A network line driver configured for receiving a differential pair of signals and driving said differential pair of signals onto a network medium, comprising:

a first driver circuit receiving a first current signal as a signal of said differential pair of signals, and including

a first circuit operable in both a low transmission frequency mode and a high transmission frequency mode and connected to (i) a potential source, (ii) a first input node receiving said first current signal, and (iii) a first output node providing a first output current, and

a second circuit operable in only the high transmission frequency mode and connected to the potential source and controllably connected to the first input node; and

a second driver circuit receiving a second current signal as another signal of said differential pair of signals, and including

a third circuit operable in both the low and high transmission frequency modes and connected to (i) the potential source, (ii) a second input node receiving said second current signal, and (iii) a second output node providing a second output current, and

a fourth circuit operable in only the high transmission frequency mode and connected to the potential source and controllably connected to the second input node.

16. The network line driver according to claim 15, wherein

the first circuit of the first driver is a current mirror having a first transistor and a second transistor, said first transistor has a first conductor connected to said potential source, a second conductor connected to said first input node and a gate connected to said first input node, and said second transistor has a first conductor connected to said potential source, a second conductor connected to said first output node and a gate connected to the first input node;

and

the third circuit of the second driver is a current mirror having a third transistor and a fourth transistor, said third transistor has a first conductor connected to said potential source, a second conductor connected to said second input node and a gate connected to said second input node, and said fourth transistor has a first conductor connected to said potential source, a second conductor connected to said second output node and a gate connected to the second input node.

17. The network line driver according to claim 16, wherein

the second circuit of the first driver comprises a fifth transistor having a first conductor connected to said potential source, a second conductor connected to the first input node, and a gate controllably connected to the first input node,

in said low transmission frequency mode

said potential source is at a first level,

a first input current is provided to said first input node, and

said first circuit provides a first output current with a first current gain to said first output node, and

in said high frequency mode,

said potential source is at a second lower level,

a second lower input current is provided to said first input node, and

said first and second circuits provide a second output current less than the first output current, with a second current gain lower than the first current gain, to said first output node;

and

the fourth circuit of the second driver comprises a sixth transistor having a first conductor connected to said potential source, a second conductor connected to the second input node, and a gate controllably connected to the second input node,

in said low transmission frequency mode

said potential source is at the first level,

the first input current is provided to said second input node, and

said third circuit provides the first output current with the first current gain to said second output node, and

in said high frequency mode,

said potential source is at the second level,

the second input current is provided to said second input node, and

said third and fourth circuits provide the second output current with the second current gain to said second output node.

18. The network line driver according to claim 17, wherein

the second circuit of the first driver further comprises

an inverter receiving a transmission frequency mode selection signal and outputting an inverted transmission frequency mode selection signal,

a seventh transistor having a first conductor connected to the source of potential, a second conductor connected to the gate of the fifth transistor and a gate receiving the transmission frequency mode selection signal, and

a eighth transistor having a first conductor connected to the first input node, a second conductor connected to the gate of the fifth transistor and to the second conductor of the seventh transistor, and a gate receiving the inverted transmission frequency mode selection signal;

and

the fourth circuit of the second driver further comprises

a ninth transistor having a first conductor connected to the source of potential, a second conductor connected to the gate of the sixth transistor and a gate receiving the transmission frequency mode selection signal, and

a tenth transistor having a first conductor connected to the second input node, a second conductor connected to the gate of the sixth transistor and to the second conductor of the ninth transistor, and a gate receiving the inverted transmission frequency mode selection signal from the second circuit of the first driver.

19. The network driver according to claim 18, wherein the first through tenth MOS transistors are all the same type MOS transistor.

20. The network line driver according to claim 15, wherein the low transmission frequency mode is 10 Mb/s and the high transmission frequency mode is 100 Mb/s.

21. The network line driver according to claim 20, wherein in the low transmission frequency mode the first and second drivers have to drive about 1.8 to 2.5 volts, and in the high transmission frequency mode, the first and second drivers have to drive about 1 volt.