Method for displaying data on a video display

• US 6,160,561 A
• Filed: 09/12/1996
• Issued: 12/12/2000
• Est. Priority Date: 09/12/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micro Electronics Incorporated
• Inventors: Klein, Dean A.
• Primary Examiner(s): LAO, LUNYI
• Application Number:
  US08/712,893
• Time in Patent Office: 1,552 Days
• Field of Search: 345/132, 345/501, 345/521, 345/507, 345/508, 345/103, 345/7-9, 345/1-3, 345/516, 714/39
• US Class Current: 345/536
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/399 using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Abstract

In a method and apparatus for displaying data on a video display that is controlled by a video controller, the video controller is coupled to a high-speed memory and a low-speed memory. The memories have separate data paths. A video address corresponding to a location on the video display is received. If a specified address bit is in a first state, then data is displayed from the high-speed memory. If the specified address bit is in a second state, then data is displayed from the low-speed memory. The specified address bit may be a high order address bit that is not utilized by a conventional VGA controller to transmit address information.

Claims

1. A method for displaying data on a video display comprising:

(a) using a video controller to receive a video address corresponding to a location on a video display, said video address including a plurality of video address bits;

(b) using the video controller to read video data at a first rate over a first datapath from a high-speed memory and to display the read data on a first part of the video display if a specified video address bit is in a first state; and

(c) using the video controller to read video data at a second rate over a second datapath from a low-speed memory and to display the read data on a second part of the video display if the specified video address bit is in a second state.

2. The method of claim 1, wherein the specified bit comprises a high order video address bit for a VGA video mode.

3. The method of claim 1, wherein the separate data paths can conduct data simultaneously.

4. The method of claim 1, wherein the act of using the video controller to display comprises using a cathode ray tube.

5. The method of claim 1, wherein the act of using the video controller to display comprises using a flat panel display.

6. The method of claim 1, wherein the act of using the video controller to display data from a high-speed memory comprises using a high-speed memory having a capacity less than the total amount of data to be displayed on the video display.

7. A method for displaying data on a video display comprising:

(a) receiving, by a video controller, a video address corresponding to a location on a video display, said video address including a plurality of video address bits;

(b) reading, by a video controller, data at a first rate over a first data path from a high-speed memory coupled to the video controller if a specified video address bit is in a first state and displaying the data from the high-speed memory on a first portion of the video display; and

(c) reading, by the video controller, data at a second rate over a second data path from a low-speed memory coupled to the video controller if the specified video address bit is in a second state and displaying the data from the low-speed mnemory on a second portion of the video display.

8. The method of claim 7, wherein the specified bit comprises a high order video address bit for a VGA video mode.

9. The method of claim 7, wherein the act of displaying uses a cathode ray tube.

10. The method of claim 7, wherein the act of displaying uses a flat panel display.

11. The method of claim 7, wherein the act of reading from the high-speed memory comprises reading from a high-speed memory having a capacity less than the total amount of data to be displayed on the video display.

12. A method for use in a system having a video display, comprising:

storing a first portion of video data for display on the video display in a high-speed memory which is coupled to a video controller over a first data path;

storing a second portion of video data for display on the video display in a low-speed memory which is coupled to said video controller over a second data path; and

alternately accessing the first and second video data portions in response to received video addresses to retrieve video data for display on the video display to reduce bandwidth requirement for the video data in the low-speed memory.