Ball grid array package and method using enhanced power and ground distribution circuitry

• US 6,160,705 A
• Filed: 05/05/1998
• Issued: 12/12/2000
• Est. Priority Date: 05/09/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Stearns, William P., Hassanzadeh, Nozar
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): CHERVINSKY, BORIS LEO
• Application Number:
  US09/072,710
• Time in Patent Office: 952 Days
• Field of Search: 361/690, 361/692, 361/693, 361/704-710, 361/717-719, 361/749, 361/772, 361/773, 361/774, 361/764, 257/691, 257/693, 257/697, 257/707, 257/713, 257/723, 257/738, 257/712, 174/254, 174/252, 174/16.3, 165/80.3, 165/185
• US Class Current: 361/704
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01028 Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10162 with a square active surface
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15321 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A structure (10) is provided that is fabricated as a ball grid array substrate that includes a substrate dielectric (14), a power ring (18), a ground ring (20), a plurality of traces, and a second metal layer (16). The substrate dielectric (14) includes a first side, a second side, and a cavity formed therein. The power ring (18), the ground ring (20), and the plurality of traces are provided on the first side of the substrate dielectric (14). The plurality of traces, for example, may include a signal connection (22), a ground connection (24), and a power connection (26). The second metal layer (16) is provided on the second side of the substrate dielectric (14) and is electrically coupled to the first side. For example, the second metal layer (16) may serve as an active ground plane and electrically couple to a variety of ground connections, such as the ground connection (24), and the ground ring (20) through vias in the substrate dielectric (14). The present invention also provides a method for forming a ball grid array package using the structure (10).

Claims

1. A ball grid array substrate package comprising:

a substrate dielectric having a first side, a second side, and a cavity formed therein and extending from said first side to said second side;

a power ring provided on the first side;

a ground ring provided on the first side;

a plurality of traces provided on the first side;

a solid, contiguous metal layer provided on the second side of the substrate dielectric, the metal layer electrically coupled to the first side; and

wherein a semiconductor die is situated in said cavity in said substrate dielectric.

2. The ball grid array substrate of claim 1, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring through a metallized via.

3. The ball grid array substrate of claim 1, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring through the cavity.

4. The ball grid array substrate of claim 1, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring.

5. The ball grid array substrate of claim 4, wherein the metal layer that serves as the ground plane is electrically coupled to a finger trace of the plurality of traces to serve as a ground connection and to provide signal isolation between traces of the plurality of traces.

6. The ball grid array substrate of claim 4, wherein a select number of the plurality of traces serve as ground connections and are electrically coupled to one another on the first side, the select number of the plurality of traces that serve as ground connections are electrically coupled to the metal layer on the second side through a metallized via.

7. The ball grid array substrate of claim 1, wherein each of the traces of the plurality of traces serve as either a ground connection, a signal connection, or a power connection.

8. The ball grid array substrate of claim 1, wherein the metal layer serves as a power plane and is electrically coupled to the power ring through a metallized via.

9. The ball grid array substrate of claim 1, wherein the metal layer serves as a power plane and is electrically coupled to the power ring through the cavity.

10. The ball grid array substrate of claim 1, wherein the power ring includes extension branches.

11. The ball grid array substrate of claim 1, wherein the power ring includes segments.

12. The ball grid array substrate of claim 1, further comprising:

an array of solder balls provided on the first side of the substrate dielectric, the array of solder balls coupled to the plurality of traces to provide an external connection to the ball grid array substrate.

13. A semiconductor package comprising:

a heat spreader/stiffener;

a ball grid array substrate having a ground ring, a power ring, a plurality of traces, and an array of solder balls on a first side of a substrate dielectric, the array of solder balls coupled to the plurality of traces to provide an external connection to the ball grid array package, the ball grid array substrate having a solid, contiguous metal layer on a second side of the substrate dielectric that is electrically coupled to the first side and is mounted to the heat spreader/stiffener, the substrate dielectric having a cavity formed therein and extending from said first side to said second side; and

a die mounted to the heat spreader/stiffener within the cavity of the ball grid array substrate, the die having at least one signal die bond pad coupled to a trace of the plurality of traces, at least one power die bond pad coupled to the power ring, and at least on ground die bond pad coupled to the ground ring.

14. The semiconductor package of claim 13, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring through a metallized via.

15. The semiconductor package of claim 13, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring through the cavity.

16. The semiconductor package of claim 13, wherein the metal layer serves as a ground plane and is electrically coupled to the ground ring.

17. The semiconductor package of claim 16, wherein the metal layer that serves as the ground plane is electrically coupled to a finger trace of the plurality of traces to serve as a ground connection and to provide signal isolation between traces of the plurality of traces.

18. The semiconductor package of claim 13, wherein each of the traces of the plurality of traces serve as either a ground connection, a signal connection, or a power connection.

19. The semiconductor package of claim 13, wherein the metal layer serves as a power plane and is electrically coupled to the power ring through a metallized via.

20. The semiconductor package of claim 13, wherein the metal layer serves as a power plane and is electrically coupled to the power ring through the cavity.

21. A method for forming a structure comprising the steps of:

providing a substrate having a first metal layer on a first surface of a substrate dielectric and a solid, contiguous second metal layer on a second surface of the substrate dielectric;

forming a power ring, a ground ring, and a plurality of traces using the first metal layer, each of the plurality of traces serving as either a ground connection, a signal connection, or a power connection;

forming a cavity in the substrate so as to extend from said first surface to said second surface;

forming vias that couple portions of the first metal layer to the second metal layer; and

placing a semiconductor die in said cavity in said substrate.

22. The method of claim 21, wherein the forming vias step includes providing metallized vias that electrically couple the ground ring to the second metal layer, and that electrically couple the traces serving as ground connections to the second metal layer that serves as a ground plane.

23. The method of claim 21, wherein the forming vias step includes providing metallized vias that electrically couple the power ring to the second metal layer, and that electrically couple the traces serving as power connections to the second metal layer that serves as a power plane.

24. The method of claim 21, further comprising the step of:

forming solder balls to attach to select traces of the plurality of traces.

25. The method of claim 21, including additional steps to form a ball grid array package, the additional steps comprising:

mounting the substrate to a heat spreader/stiffener;

mounting a die to the heat spreader/stiffener through the cavity in the substrate; and

coupling a signal die bond pad of the die to a trace of the plurality of traces.

26. The method of claim 25, further comprising the steps of:

sealing the die cavity; and

forming solder balls to attach to select traces of the plurality of traces.