Fibre channel switching system and method

• US 6,160,813 A
• Filed: 03/21/1997
• Issued: 12/12/2000
• Est. Priority Date: 03/21/1997
• Status: Expired due to Term

• Current Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Original Assignee: Brocade Communications Systems, Inc. (Broadcom, Inc.)
• Inventors: Banks, David C., Ramsay, Paul, Stoevhase, Bent, Farnworth, Steven L.
• Primary Examiner(s): Vu, Huy C.
• Assistant Examiner(s): BOAKYE, ALEXANDER O
• Application Number:
  US08/823,025
• Time in Patent Office: 1,362 Days
• Field of Search: 370/380, 370/384, 370/392, 370/402, 370/412, 370/422, 370/429, 395/182.02, 395/200.69
• US Class Current: 370/422
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/205 Quality of Service based
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/357 Fibre channel switches

Abstract

A modular Fibre Channel switch includes a data switching path and a message switching path to provide logical point to point connections between switch ports. The data switching path includes a bank of shared SRAM memory devices that are accessed in a time-sliced protocol by each switch port. A receiving switch port writes a data frame to the bank of shared SRAM and the transmitting switch port then reads the data frame from the shared SRAM thereby effecting the logical point to point connection. Because the switch port includes a frame logic circuit that allows for an arbitrary start of frame address, each frame can be written to the first available DRAM device thus eliminating the need to buffer the data frame while waiting for a predetermined DRAM device to cycle in the time sliced protocol. The message switching path includes a message crossbar switch that is barrel shifted in a time sliced fashion to effect message passing among the switch ports. The switch includes a motherboard containing an embedded G_-- Port ASIC, a message crossbar switch to handle message passing and shared memory that is used to perform data switching. The switch also includes a central processing unit daughter board and external switch port daughter boards.

Claims

1. A network switching system having a plurality of ports for switching data from a first port to a second port, comprising:

a message path including;

a crossbar switch having a plurality of connectivity states coupled to each port; and

a message controller coupled to each port and to the crossbar switch to control access to the crossbar switch; and

a data path including;

a central memory including a plurality of memory modules coupled to each port; and

a memory access controller coupled to each port for controlling access of the plurality of memory modules by the ports, wherein the memory access controller includes;

a counting circuit having a count output and a control input;

an index pulse generator having a pulsed output coupled to the control input of the counter;

a register storing a port number; and

a processing circuit having a first input coupled to the counting circuit and a second input coupled to the register and having an output indicating a memory module offset.

2. A network switching system having a plurality of ports for switching data from a first port to a second port, comprising:

a message path including;

a crossbar switch having a plurality of connectivity states coupled to each port; and

a message controller coupled to each port and to the crossbar switch to control access to the crossbar switch;

wherein the message controller includes;

a counting circuit having a count output and a control input;

an index pulse generator having a pulsed output coupled to the control input of the counter; and

a processing circuit having a first input coupled to the counting circuit and an output indicating the connectivity state of the crossbar switch; and

a data path including;

a central memory including a plurality of memory modules coupled to each port; and

a memory access controller coupled to each port for controlling access of the plurality of memory modules by the ports.

3. A network switching system for temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the system comprising:

a central memory comprising;

a plurality of memory modules; and

a scratch area;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

a port circuitry which,

responsive to a data frame being available for writing to the memory module, writes a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules when the data frame is available; and

responsive to no data frame being available for writing to the memory module, writes to the scratch area during the timeslot allocated for writing from the receive port to one of the memory modules.

4. A network switching system for temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the system comprising:

a central memory including a plurality of memory modules;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module, wherein the data path control circuit couples the receive port to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory; and

a port circuitry for writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules.

5. A network switching system for temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the system comprising:

a central memory including a plurality of memory modules;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

a port circuitry for writing a first portion of the data frame to a first memory module during a first available timeslot; and

further for writing the remaining portions of the data frame to other memory modules during subsequent timeslots.

6. A network switching system for temporarily storing a data frame received at a receive port of a plurality of fiber optic ports, the system comprising:

a central memory including a plurality of memory modules;

a data path control circuit for

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port; and

a port circuitry for

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules, wherein for each memory module the timeslots allocated for writing to the memory module are contiguous in time; and

reading a portion of the data frame from the individual memory modules to the transmit port during the timeslot allocate for such reading, wherein the data frame is read to the transmit port, wherein for each memory module the timeslots allocated for reading from the memory module are contiguous in time.

7. The system of claim 6 wherein the contiguous timeslots allocated for writing are separated from the timeslots allocated for reading by at least one timeslot.

8. A network switching system for retrieving a temporarily stored data frame destined for a transmit port of a plurality of fiber optic ports, the system comprising:

a central memory including a plurality of memory modules for storing a data frame across the memory modules;

a data path control circuit for sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port, wherein the data path control circuit couples the transmit port to the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port; and

a port circuitry for reading a portion of the data frame from the memory module to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port.

9. A network switching system for switching a data frame from a receive port of a plurality of fiber optic ports to a transmit port of the plurality of fiber optic ports, the system comprising:

a central memory including a plurality of memory modules, and wherein the central memory is subdivided into a plurality of frame buffers, each frame buffer including a portion of each memory module;

a data path control circuit for sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module and further for sequentially coupling the transmit port to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port, wherein the data path control circuit couples each port to each memory module in a regular sequence for writing to the memory module and couples each port to each memory module in a regular sequence for reading from the memory module, all of the timeslots being of equal duration;

a receive port circuitry for writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written to one of the frame buffers;

a message path for sending a message from the receive port to the transmit port indicating availability of the data frame in the central memory; and

a transmit port circuitry for, responsive to receipt of the message indicating availability of the data frame, reading the portions of the data frame from the ones of the memory modules to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port.

10. The system of claim 9 wherein:

a first portion of the data frame is written to a first memory module during a first available timeslot;

the remaining portions of the data frame are written to other memory modules during subsequent timeslots; and

the message identifies the first memory module and the frame buffer to which the data frame is written.

11. The system of claim 9 wherein the data path control circuit couples the receive port to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory and couples the transmit port to the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port.

12. In a network switching system comprising a plurality of fiber optic ports;

and a central memory including a plurality of memory modules, a method for temporarily storing a data frame comprising;

receiving a data frame at a receive port of the plurality of ports;

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules;

designating a portion of the central memory as a scratch area; and

writing to the scratch area during the timeslot allocated for writing from the receive port to one of the memory modules when no data frame is available for writing to the memory module.

13. In a network switching system comprising a plurality of fiber optic ports;

and a central memory including a plurality of memory modules, a method for temporarily storing a data frame comprising;

receiving a data frame at a receive port of the plurality of ports;

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module, wherein the receive port is coupled to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory; and

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules.

14. In a network switching system comprising a plurality of fiber optic ports;

and a central memory including a plurality of memory modules, a method for temporarily storing a data frame comprising;

receiving a data frame at a receive port of the plurality of ports;

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module; and

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules, comprising;

writing a first portion of the data frame to a first memory module during a first available timeslot; and

writing the remaining portions of the data frame to other memory modules during subsequent timeslots.

15. In a network switching system comprising a plurality of fiber optic ports;

and a central memory including a plurality of memory modules, a method for temporarily storing a data frame comprising;

receiving a data frame at a receive port of the plurality of ports;

sequentially coupling the receive port to ones of the memory modules during a timeslot allocated for writing from the receive port to the memory module;

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written across the memory modules, and wherein, for each memory module the timeslots allocated for writing to the memory module are contiguous in time;

sequentially coupling a transmit port of the plurality of ports to ones of the memory modules during a timeslot allocated for reading from the memory module to the transmit port; and

reading a portion of the data frame from the individual memory modules to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port, and wherein, for each memory module, the timeslots allocated for reading from the memory module are contiguous in time.

16. The method of claim 15 wherein the contiguous timeslots allocated for writing are separated from the timeslots allocated for reading by at least one timeslot.

17. In a network switching system comprising a plurality of fiber optic ports;

and a central memory including a plurality of memory modules, a method for retrieving a data frame temporarily stored across the memory modules, the method comprising;

sequentially coupling a transmit port to ones of the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port; and

reading a portion of the data frame from the memory module to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port.

18. In a network switching system comprising a plurality of fiber optic ports, and a central memory comprising a plurality of memory modules, a method for switching a data frame from a receive port of the plurality of ports to a transmit port of the plurality of ports, the method comprising:

subdividing the central memory into a plurality of frame buffers, each frame buffer including a portion of each memory module;

receiving a data frame at a receive port;

sequentially coupling the receive port to ones of the memory modules in a regular sequence, during a timeslot allocated for writing from the receive port to the memory module;

writing a portion of the data frame from the receive port to ones of the memory modules during the timeslot allocated for such writing, wherein the data frame is written to one of the frame buffers;

sending a message from the receive port to the transmit port indicating availability of the data frame in the central memory;

sequentially coupling the transmit port to ones of the memory modules in a regular sequence, during a timeslot allocated for reading from the memory module to the transmit port;

responsive to receipt of the message indicating availability of the data frame, reading the portions of the data frame from the ones of the memory modules to the transmit port during the timeslot allocated for such reading, wherein the data frame is read to the transmit port; and

wherein all of the timeslots are of equal duration.

19. The method of claim 18 wherein:

the step of writing a portion of the data frame from the receive port to ones of the memory modules comprises;

writing a first portion of the data frame to a first memory module during a first available timeslot; and

writing the remaining portions of the data frame to other memory modules during subsequent timeslots; and

the message identifies the first memory module and the frame buffer to which the data frame is written.

20. The method of claim 18 wherein:

the step of sequentially coupling the receive port to ones of the memory modules comprises coupling the receive port to the memory modules frequently enough to support continuous writing of data from the receive port to the central memory; and

the step of sequentially coupling the transmit port to ones of the memory modules comprises coupling the transmit port to the memory modules frequently enough to support continuous reading of data from the central memory to the transmit port.