System and method for extracting and restoring a video buffer from/to a video acquisition cycle

• US 6,161,154 A
• Filed: 11/26/1997
• Issued: 12/12/2000
• Est. Priority Date: 11/26/1997
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Schultz, Kevin L., Repich, Dan
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US08/979,589
• Time in Patent Office: 1,112 Days
• Field of Search: 710/22, 710/52-56, 709/236, 709/250, 711/156
• US Class Current: 710/56
• CPC Class Codes: G06T 1/0007 Image acquisition

Abstract

A system and method for dynamically re-programming the acquisition cycle of a video acquisition system. The video acquisition system comprises a host computer and a video source. The host computer comprises a CPU, a system memory, and a video capture board. The video capture board receives a video signal from the video source. The video signal comprises a sequence of frames. The video capture board includes a DMA Controller which writes video frames to system memory under the control of a circularly linked list of commands. The linked list contains a plurality of sublists, each of which schedules the DMA transfer of a video frame to a corresponding video buffer in system memory. By removing a sublist from the linked list, a video buffer is removed from the set of buffers targeted for data transfer by the DMA Controller. By adding a sublist to the linked list, a video buffer is restored to the targeted set. A current or recently completed video buffer is removed from the targeted set in response to a request asserted by an application program.

Claims

1. An image acquisition system for acquiring digital video data from a video sequence and storing the frames in a computer memory, the image acquisition system comprising:

a buffer memory which receives and stores the digital video data;

a computer memory which includes a plurality of frame buffers each operable to store digital video data corresponding to a video frame;

a direct memory access (DMA) controller coupled to the buffer memory which is operable to transfer digital video data from the buffer memory to the computer memory;

a frame buffer access list which stores information indicating availability of said plurality of frame buffers in said computer memory;

wherein said direct memory access controller is operable to access said frame buffer access list and uses values in said frame buffer access list to transfer said digital video data from said buffer memory to available ones of said frame buffers in the computer memory, wherein said values in said frame buffer access list determine said available ones of said frame buffers;

wherein said values in said frame buffer access list are manipulable to exclude one or more selected frame buffers of the plurality of frame buffers from receiving said digital video data, wherein after a first manipulation of the frame buffer access list to exclude the one or more selected frame buffers from the plurality of frame buffers, said direct memory access controller continues to transfer said digital video data from said buffer memory to remaining available ones of the plurality of frame buffers.

2. The system of claim 1, wherein the image acquisition system is comprised in a computer system;

wherein the image acquisition system further comprises;

a CPU coupled to the computer memory which is operable to process digital video data stored in one or more of said frame buffers in the computer memory;

wherein the CPU is operable to perform said first manipulation of the frame buffer access list to exclude the one or more selected frame buffers from the plurality of frame buffers.

3. The system of claim 2,

wherein the CPU is operable to process digital video data in said one or more selected frame buffers while said remaining available frame buffers continue to receive digital video data from the buffer memory.

4. The system of claim 3, wherein the CPU is operable to perform a second manipulation of said values in said frame buffer access list to restore availability of said one or more selected frame buffers in the computer memory for receiving new digital video data from said buffer memory.

5. The system of claim 1, wherein said frame buffer access list is comprised in the computer memory.

6. The system of claim 1, wherein said frame buffer access list comprises a linked list of references to said plurality of frame buffers in the computer memory;

wherein a reference in said linked list is removed to exclude the corresponding frame buffer in the computer memory from the plurality of frame buffers;

wherein the reference is added to the linked list to restore availability of the corresponding frame buffer in the computer memory for receiving new digital video data from said buffer memory.

7. The system of claim 1, wherein the system includes an interface card comprised in a computer system, wherein the buffer memory and the DMA controller are comprised on the interface card.

8. The system of claim 1, wherein said first manipulation excludes a last received frame buffer in the computer memory.

9. The system of claim 1, further comprising a CPU which is configured (a) to identify a first frame buffer which is currently receiving digital video data from said buffer memory, (b) to wait until the completion of a digital video data transfer to the first frame buffer, and (c) to perform the first manipulation to exclude the first frame buffer from the plurality of frame buffers.

10. A method for acquiring digital video data from a video sequence into a computer memory which comprises a plurality of frame buffers, the method comprising:

receiving digital video data;

storing the digital video data in a buffer memory;

a direct memory access controller transferring said digital video data from the buffer memory to available ones of said frame buffers, wherein each of said frame buffers is sufficient to store a video frame;

wherein said transferring is controlled by a frame buffer access list, wherein said frame buffer access list stores information which indicates availability of said plurality of frame buffers for digital video data transfer;

manipulating values in said frame buffer access list to exclude one or more selected frame buffers of the plurality of frame buffers from receiving said digital video data; and

said direct memory access controller continuing to transfer said digital video data from said buffer memory to remaining available ones of the plurality of frame buffers after said manipulating, wherein said one or more selected frame buffers do not receive said digital video data.

11. The method of claim 10, wherein said transferring comprises:

examining said frame buffer access list;

determining which of said frame buffers are available in response to said examining; and

transferring said digital video data to one or more of said plurality of frame buffers determined to be available in said determining.

12. The method of claim 11, wherein said examining said frame buffer access list identifies a most recently completed frame buffer, and wherein said manipulating values in said frame buffer access list disables availability of said most recently completed frame buffer for receiving new digital video data from said buffer memory.

13. The method of claim 11, wherein said examining said frame buffer access list identifies a current frame buffer, and wherein said manipulating values in said frame buffer access list disabled availability of said current frame buffer for receiving new digital video data from said buffer memory.

14. The method of claim 10, further comprising:

processing digital video data stored in said one or more selected frame buffers.

15. The method of claim 10, wherein the method operates in an image acquisition system including a CPU;

wherein the CPU performs said manipulating of said values in said frame buffer access list and processes said digital video data stored in said one or more selected frame buffers.

16. The method of claim 11, further comprising:

manipulating said values in said frame buffer access list to restore availability of said one or more selected frame buffers for receiving new digital video data from said buffer memory.

17. The method of claim 10, wherein said frame buffer access list comprises a linked list of references to said plurality of frame buffers in the computer memory;

wherein removing a reference in said linked list excludes a corresponding frame buffer in the computer memory from the plurality of frame buffers;

wherein restoring the reference to the linked list restores availability of the corresponding frame buffer for receiving new digital video data from said buffer memory.

18. An image acquisition system comprising:

a processor;

a system memory;

a direct memory access (DMA) controller configured to read and execute nodes in a circularly-linked control list stored in system memory, wherein the DMA controller (a) receives a first stream of digitized video frames and (b) transfers the first stream of digitized video frames to a set of video buffers in system memory under the control of the control list;

wherein the control list comprises a set of sublists in one-to-one correspondence with the set of video buffers in system memory, wherein each of the sublists contains one or more transfer nodes, wherein each of said one or more transfer nodes (c) specifies a target address in system memory and a data transfer length and (d) instructs the DMA controller to transfer video data comprising at least a portion of one of said digitized video frames to system memory starting at the target address, wherein the data transfer length defines the number of data units to be transferred to system memory starting at the target address;

wherein the processor is configured to alter the linkage structure of the control list to remove a first sublist from control list so that a first video buffer corresponding to the first sublist is no longer targeted for transfers by the DMA controller.

19. A method comprising:

receiving a first stream of video data and buffering the first stream of video data in a First-In-First-Out buffer (FIFO);

performing a series of direct memory access (DMA) transfers from the FIFO to a set of video buffers in a system memory under the control of a circularly-linked control list stored in the system memory, wherein the control list comprises a set of sublists in one-to-one correspondence with the set of video buffers in system memory, wherein each of the sublists contains one or more transfer nodes, wherein each of said one or more transfer nodes specifies a target address in system memory and a data transfer length for one of said series of DMA transfers;

altering the linkage structure of the control list to remove a first sublist from control list so that a first video buffer corresponding to the first sublist is no longer targeted by any of said series of DMA transfers.