Multiple processor, distributed memory computer with out-of-order processing

• US 6,161,170 A
• Filed: 04/21/1999
• Issued: 12/12/2000
• Est. Priority Date: 06/27/1997
• Status: Expired due to Term

• Current Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Inventors: Goodman, James R., Burger, Douglas C., Kaxiras, Stefanos
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US09/296,027
• Time in Patent Office: 601 Days
• Field of Search: 717/9, 717/4, 717/56, 712/28, 712/30, 712/11, 712/27, 712/214
• US Class Current: 712/30
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5016 the resource being the memory

Abstract

A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

Claims

1. A method of executing a program made up of a set of instructions and data, the instructions having a program order, on a computer system having a plurality of processor/memory units communicating on a common interconnect, the method comprising the steps of:

(a) profiling the program to determine first portions of the program statistically more likely to be executed in a predetermined period of operation of the program than second portions of the program; and

(b) dividing the portions of the program among the processor/memory units so that the first portions are loaded into more than one processor/memory unit; and

(c) executing all the instructions on each of the processor/memory units by causing a first processor/memory unit having a portion of the set not loaded into other processor/memory units to communicate that portion over the common interconnect to the other processor/memory units without a request by the other processor/memory units for the portions.