Non-intrusive in-system debugging for a microcontroller with in-system programming capabilities using in-system debugging circuitry and program embedded in-system debugging commands

• US 6,161,199 A
• Filed: 12/12/1997
• Issued: 12/12/2000
• Est. Priority Date: 12/12/1997
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: UBICOM Incorporated (Qualcomm, Inc.)
• Inventors: Cheng, Chuck C. W., Gracey, Charles M. III, Szeto, Kinyue
• Primary Examiner(s): Follansbee, John A.
• Assistant Examiner(s): EL HADY, NABIL M
• Application Number:
  US08/989,830
• Time in Patent Office: 1,096 Days
• Field of Search: 395/500, 712/220-232, 710/129, 714/30-36, 714/38, 364/140.09, 711/103, 703/28
• US Class Current: 714/30
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

An in-system debugging (ISD) capability is incorporated into a production microcontroller. The ISD capability is incorporated without the costly addition of any extra pins to read out the data for debugging by using the oscillator pins of the production microcontroller to read out the data. Building such an ISD capability into the microcontroller, enables debugging to be performed on the actual production board (instead of a special debug board) having the actual production microcontroller (instead of a bond-out microcontroller). This allows designers to debug programming using the actual production system instead of an emulation system.

Claims

1. An in-system debug (ISD) apparatus for debugging a program residing in a microcontroller of a microcontroller system, the apparatus comprising:

a system board of the microcontroller system;

a microcontroller having built-in ISI) hardware circuitry mounted on the system board having a pin that provides a first function during a normal mode of operation and a second data relay function during an internally controlled in-system debugging mode of operation for relaying data generated by the microcontroller responsive to executing the program to an external monitoring system without affecting the normal I/O operations of the microcontroller, and

the external monitoring system, comprising;

an ISD interface board coupled to the system board for receiving the data generated by the microcontroller; and

a computer system coupled to the ISD interface board, the computer system comprising an ISD software module for monitoring the data generated by the microcontroller.

2. The apparatus of claim 1, wherein the built-in ISD hardware is serially coupled to the pin to receive data relayed serially from the pin.

3. The apparatus of claim 2, wherein the ISD interface board is serially coupled to the pin to receive data relayed serially from the pin.

4. The apparatus of claim 3, wherein the pin functions as an oscillator pin during normal operation of the microcontroller.

5. The apparatus of claim 4, wherein the microcontroller further comprises a register which is serially coupled to the pin, the register being further coupled to the built-in ISD hardware.

6. The apparatus of claim 5, wherein the register comprises a working register (accumulator) during normal (non-programming and non-debugging) operation of the microcontroller.

7. The apparatus of claim 5, wherein the microcontroller further comprises a storage unit for a carry bit, and the storage unit is serially coupled between the pin and the register.

8. The apparatus of claim 1, wherein during normal operation, the system board is adapted to receive information from an external system and to control the external system using the information.

9. The apparatus of claim 8, wherein the microcontroller orchestrates the normal operation of the system board.

10. The apparatus of claim 1, further comprising an ISD software module in memory of the computer system for communicating with the built-in ISD hardware circuitry in the microcontroller.

11. The apparatus of claim 1, wherein the microcontroller further comprises a plurality of debug register stacks, each register stack having a corresponding debug register.

12. The apparatus of claim 11, wherein each register stack comprises a top stack address containing present contents of the corresponding register, a middle stack address containing most-recently-saved contents from the corresponding register, and a lower stack address containing next-to-most-recently-saved contents from the corresponding register.

13. The apparatus of claim 12, wherein for each register stack a normal (non-debug) interrupt causes contents from the top stack address of the corresponding register to be pushed to middle stack address of the corresponding register.

14. The apparatus of claim 13, wherein for each register stack a debug interrupt causes contents from the middle stack address of the corresponding register to be pushed to lower stack address of the corresponding register, and contents from the top stack address of the corresponding register to be pushed to middle stack address of the corresponding register.

15. The apparatus of claim 11, wherein the plurality of register stacks includes a register stack corresponding to a working register.

16. The apparatus of claim 11, wherein the plurality of register stacks includes register stacks corresponding to a working register, a status register, a file select register, and a program counter register.

17. A method for in-system debugging (ISD) of a program to be loaded into a microcontroller having built-in hardware circuitry, the microcontroller having a normal mode of operation, and an in-system programming (ISP) mode of operation, the method comprising:

entering an in-system programming (ISP) mode of the microcontroller, loading the program with embedded ISD commands into an EEPROM of the microcontroller;

exiting the ISP mode of the microcontroller; and

executing the program in normal mode of operation while monitoring execution of the program by the microcontroller without affecting the normal I/O operations of the microcontroller, wherein monitoring the execution of the program is performed using an external monitoring system coupled to an ISD interface for receiving data generated by the microcontroller via a pin that provides a first function during a normal mode of operation and a second data relay function in an ISD mode of operation.

18. The method of claim 17, wherein the loading is performed serially.

19. The method of claim 17, wherein the debugging command comprises a command from a group of commands, said group including commands to add a breakpoint, request single-stepping, and read a register.

20. The method of claim 17, wherein the monitoring is performed via two pins adapted to function as oscillator pins during normal operation of the microcontroller.