Semiconductor non-volatile memory device having a NAND cell structure

• US 6,163,048 A
• Filed: 04/16/1998
• Issued: 12/19/2000
• Est. Priority Date: 10/25/1995
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hirose, Ryan T., Lancaster, Loren T.
• Primary Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US09/051,700
• Time in Patent Office: 978 Days
• Field of Search: 257/315, 257/316, 257/322, 257/324, 257/326, 365/104, 365/184, 365/185.01, 365/185.05, 365/185.11, 365/185.13, 365/185.17, 365/185.18, 365/185.24, 365/185.25, 365/185.26 , 365/185.27, 365/185.28, 365/185.29, 365/189.01, 365/189.09, 365/222
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A NAND stack array (95'"'"') is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

Claims

1. A non-volatile semiconductor device comprising:

a semiconductor substrate;

data transmission bit lines arranged on said substrate;

a memory cell section including a plurality of memory units, each connected on a first end to one of said bit lines and on a second end to a common reference node, at least one said memory unit comprising addressable memory transistors, each of said memory transistors having a source, node a drain, node a gate, and a charge storage layer that has programmable memory states that produce a first depletion threshold voltage of magnitude less than a magnitude of a supply voltage when the memory transistor is programmed and a different threshold voltage when the memory transistor is erased;

and at least one timer circuit to generate an output logic signal to request a data refresh operation no later than when charge stored on charge storage layers associated therewith can no longer be detected, said timer circuit comprising a transistor timing element having a source, a drain, a gate, and a charge storage layer that has programmable memory states.

2. The device of claim 1 wherein said device further comprises biasing circuitry for applying selected read biasing voltages to said memory units including a reference voltage of magnitude no greater than the magnitude of said supply voltage and greater than the magnitude of said first threshold voltage, the reference voltage being applied to said reference node, and a voltage greater than said reference voltage applied to said first end of said memory unit;

sensing circuitry for sensing a current generated at said first end of said memory unit in accordance with the programmable state of said charge storage layer of said addressable memory transistor;

circuitry for applying selected erase biasing voltages to said memory units to selectively erase memory transistors connected to a single selected word line;

and circuitry for applying selected write biasing voltages to said memory units to selectively write data into memory transistors wired in common on a single selected word line.

3. The device of claim 2 wherein said device further comprises a timer controller to provides means for initiating and controlling the execution of said data refresh operation once actuated by said timer circuit, said refresh operation comprising a controlled sequence of at least first reading selected addressable memory transistors to determine the current programmed state of said charge storage layer of each of said selected addressable memory transistors, second erasing said selected addressable memory transistors, and third programming said selected addressable memory transistors to restore said current programmed state.

4. The device of claim 3 wherein said device further comprises means to electrically partition said plurality of memory units into separate groups forming at least two blocks;

means for independently s electing blocks for a block refresh operation, said block refresh operation constituting a refresh operation performed on no more than the memory transistors within a selected block;

and a t least two timer circuits each being uniquely associated with one of said blocks for independently actuating said timer controller to execute said block refresh operation on said selected block associated therewith.

5. The device of claim 1 wherein each of said addressable memory transistors comprise a SONOS tunneling metal insulator semiconductor field effect transistor.

6. The device of claim 1 wherein each of said memory units comprise series connected addressable memory transistors and at least one selection transistor connected in series to the second end to connect said second end of each of said memory units to said reference node.

7. The device of claim 1 wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type.

8. The device of claim 1 wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a first conductivity type;

and wherein said memory cell section further comprises a first well region of a second conductivity type formed in said substrate as to surround said memory units.

9. The device of claim 8 wherein means is provided for connecting said substrate to said supply voltage and for connecting said first well to a supply reference voltage during a read operation.

10. The device of claim 1 wherein said substrate has a first conductivity type and said source and drain nodes are semiconductor regions of a second conductivity type;

and wherein said memory cell section further comprises a first well region of a first conductivity type formed in said substrate as to surround said memory units and wherein said device further comprises an additional -second well region of the second conductivity type formed in said substrate as to surround at least said first well region.

11. The device of claim 10 wherein means is provided for connecting said substrate to a supply reference voltage and for connecting said second well to said supply voltage, and for additionally connecting said first well to said supply reference voltage during a read operation.