Trench-gated vertical combination JFET and MOSFET devices

• US 6,163,052 A
• Filed: 12/16/1997
• Issued: 12/19/2000
• Est. Priority Date: 04/04/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Liu, Yowjuang W., Wollesen, Donald L.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Owens, Douglas W.
• Application Number:
  US08/991,464
• Time in Patent Office: 1,099 Days
• Field of Search: 257/334, 257/332, 257/330, 257/302, 257/287, 438/212, 438/269, 438/270, 438/268
• US Class Current: 257/334
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator (41,62) on the bottom and sidewalls of this trench, and filling the trench with highly doped polysilicon. A buried gate region (28,50) is formed by implanting the semiconductor layer, prior to top gate formation, such that the buried gate region is laterally coextensive with the mesa. An upper boundary (29,54) of the buried gate region is spaced below the bottom of the trench and spaced from the semiconductor surface. Upon application of a suitable voltage, the buried gate region and the top gate region coact to invert the conductivity type of the channel region, permitting transistor operation between the source region and the drain region.

Claims

1. A vertical combination MOSFET and JFET device, comprising:

a substrate;

a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface;

a buried gate region formed in said semiconductor layer to be spaced from said surface of said semiconductor layer and to be of a second conductivity type opposite said first conductivity type, said buried gate region having a boundary, a channel region of said device at least partly disposed adjacent to said boundary of said buried gate region;

a drain region formed adjacent said surface of said semiconductor layer to be spaced from said buried gate region by said channel region and to be of said second conductivity type;

a trench formed to extend downwardly from said surface of said semiconductor layer and having sidewalls, a bottom of said trench spaced above said boundary of said buried gate region;

a gate insulator formed to adjoin said sidewalls and said bottom of said trench;

a conductive top gate formed in said trench;

a source region formed at said surface of said semiconductor layer to be insulatively spaced from said drain region, said channel region extending from said source region to said drain region and disposed adjacent at least one of said sidewalls and adjacent said bottom of said trench, said channel region interposed between said drain region and said buried gate region, said channel region further interposed between said source region and said buried gate region; and

means for impressing a buried gate voltage on said buried gate region.

2. The device of claim 1, wherein said sidewall is endless, said top gate laterally surrounding said drain region.

3. The device of claim 1, wherein said means for impressing said buried gate voltage on said buried gate region is a buried gate connector region formed in said semiconductor layer to be of said second conductivity type and extending from said surface of said semiconductor layer to said boundary of said buried gate region.

4. The device of claim 1, wherein said substrate comprises an insulator.

5. The device of claim 1, wherein said top gate is highly doped polycrystalline silicon.

6. The device of claim 1, wherein said substrate includes a dielectric layer disposed adjacent to said buried gate region.

7. The device of claim 1, wherein said semiconductor layer is formed as a mesa of semiconductor material.

8. The device of claim 7, wherein said mesa has sidewalls, said mesa being laterally isolated by regions of dielectric material disposed adjacent said sidewalls of said mesa.

9. A complementary combination vertical MOSFET and JFET device, comprising:

a substrate;

a first semiconductor layer formed on a first area of said substrate to be of a first conductivity type and having a top surface;

a first buried gate region formed in said first semiconductor layer to have an upper boundary spaced from said top surface of said first semiconductor layer and to be of a second conductivity type opposite said first conductivity type, a first channel region of said first semiconductor layer formed to be of said first conductivity type and adjacent said first buried gate region;

a first drain region formed in said first semiconductor layer adjacent said top surface of said first semiconductor layer and to be spaced from said buried gate region of said first semiconductor layer by said first channel region, said first drain region formed to be of said second conductivity type;

a first source region formed adjacent said top surface of said first semiconductor layer and to be of said second conductivity type;

a first trench formed to extend downwardly from said top surface of said first semiconductor layer into said channel region, a bottom of said first trench spaced above said upper boundary of said first buried gate region, said first trench having at least one sidewall and laterally spacing said first drain region from said first source region;

a first gate insulator formed on said at least one sidewall;

a first conductive top gate formed in said first trench adjacent said sidewall and insulatively adjacent said first channel region;

a second semiconductor layer formed on a second area of said substrate to be of said second conductivity type and having a top surface;

a second buried gate region formed in said second semiconductor layer to be of said first conductivity type, an upper boundary of said second buried gate region spaced from said top surface of said second semiconductor layer, a second channel region of said second semiconductor layer having said second conductivity type;

a second drain region formed adjacent said top surface of said second semiconductor layer and to be spaced from said second buried gate region by said second channel region and to be of said first conductivity type;

a second trench formed from said top surface of said second semiconductor layer and extending downwardly into said second channel region, said second trench having at least one sidewall, a bottom of said trench spaced from said upper boundary of said second buried gate region;

a second gate insulator formed on said at least one sidewall and said bottom of said second trench;

a second conductive top gate formed in said second trench;

means for impressing a drain voltage on said first drain region;

means for impressing a source voltage on said second buried gate region;

means for conductively coupling together said first buried gate region with said second drain region; and

means for conductively coupling together said first and second top gates.

10. The device of claim 9, wherein said means for impressing a source voltage on said second buried gate region comprises a second buried gate connector region extending from said top surface of said second semiconductor layer to said second buried gate region, said second buried gate connector region being of said first conductivity type.

11. The device of claim 9, wherein said means for conductively coupling said first buried gate region with said second drain region comprises a first buried gate connector region formed in said first semiconductor layer to be of said second conductivity type and to extend from at least said upper boundary of said first buried gate region to said top surface of said first semiconductor layer.

12. The device of claim 9, wherein said first semiconductor layer is formed in a first mesa, said second semiconductor layer being formed in a second mesa spaced from said first mesa.

13. A vertical combination MOSFET and JFET device, comprising:

a substrate;

a semiconductor layer formed on said substrate to be of a first conductivity type and having a surface;

a buried gate region formed in said semiconductor layer to be spaced from said surface of said semiconductor layer and to be of a second conductivity type opposite said first conductivity type, said buried gate region having a boundary, a channel region of said device formed to be of said first conductivity type and to be at least partly disposed adjacent to said boundary of said buried gate region;

a drain region formed adjacent said surface of said semiconductor layer to be spaced from said buried gate region by said channel region and to be of said first conductivity type;

a trench formed to extend downwardly from said surface of said semiconductor layer and having sidewalls, a bottom of said trench spaced above said boundary of said buried gate region;

a gate insulator formed to adjoin said sidewalls and said bottom of said trench;

a conductive top gate formed in said trench;

a source region of said first conductivity type formed at said surface of said semiconductor layer to be insulatively spaced from said drain region, said channel region extending from said source region to said drain region and disposed adjacent at least one of said sidewalls and adjacent said bottom of said trench, said channel region interposed between said drain region and said buried gate region, said channel region further interposed between said source region and said buried gate region; and

means for impressing a buried gate voltage on said buried gate region.