High voltage detector to control a power supply voltage pump for a 2.5 volt semiconductor process device

• US 6,163,175 A
• Filed: 03/26/1999
• Issued: 12/19/2000
• Est. Priority Date: 03/27/1998
• Status: Expired due to Fees

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Vantiss (Lattice Semiconductor Corporation)
• Inventors: Sharpe-Geisler, Bradley A.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US09/276,990
• Time in Patent Office: 634 Days
• Field of Search: 27/77-81, 27/88, 27/89, 27/52, 27/53, 27/65, 27/66, 27/143, 27/198, 27/103, 323/315
• US Class Current: 327/77
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A high voltage detector circuit (FIG. 2) maintains a voltage (V₂) on a reference line driven by a charge pump by turning the charge pump on with a signal (PUMPON) when the reference line voltage (V₂) drops below a reference voltage (V₁) plus a CMOS transistor threshold voltage. The high voltage detector is further configured to use transistors which have a maximum gate to drain, or gate to source voltage which exceeds the pin supply voltage to the chip. The high voltage detector includes comparators made up of a series of current mirrors driven by weak current sources enabling the circuit to use a minimum amount of power.

Claims

1. A voltage detector circuit comprising:

a first transistor (208) having a source to drain path coupling a first voltage potential (V₂) line to a first node (n10);

a first current mirror comprising;

a first transistor (210) having a source to drain path coupled on a first end to the first node (n10) and on a second end to a third node (n14), and having a gate coupled to the third node (n14); and

a second transistor (214) having a source to drain path coupled on a first end to a second voltage potential (V₁) line and on a second end to a fourth node (n11), and having a gate coupled to the gate of the first transistor (210) of the first current mirror;

a second current mirror comprising;

a first transistor (212) having a source to drain path coupled on a first end to the second voltage potential (V₁) line and on a second end to a fifth node (n13), and having a gate coupled to the fifth node (n13); and

a second transistor (222) having a source to drain path coupled on a first end to the second voltage potential (V₁) line and on a second end to a sixth node (n12), and having a gate coupled to the gate of the first transistor (212) of the second current mirror;

a second transistor (204) having a source to drain path coupling the third node (n14) to V_SS, and having a gate receiving a voltage reference;

a third transistor (206) having a source to drain path coupling the fifth node (n13) to V_SS, and having a gate receiving a voltage reference; and

a third current mirror comprising;

a first transistor (230) having a source to drain path with a first end coupled to the sixth node (n12) and a second end coupled to V_SS, and having a gate coupled to the first end of its source to drain path; and

a second transistor (221) having a source to drain path with a first end coupled to the fourth node (nil) and a second end coupled to V_SS, and having a gate coupled to the gate of the first transistor (230) of the fourth current mirror, the first end of the source to drain path of the second transistor (221) for providing an output signal for the voltage detector circuit indicating if a voltage potential at the first node (n10) is greater or less than the second voltage potential (V₁) on the second voltage potential line.

2. The voltage detector of claim 1, further comprising:

a fourth transistor (200) having a source to drain path coupling the second voltage potential (V₁) line to a second node (n21), and having a gate connected to a third voltage potential (V₃) line; and

a fifth transistor (202) having a source to drain path coupling the second node (n21) to V_SS, and having a gate coupled to the second node (n21) and to the gates of the second transistor (204) and third transistor (206) to provide the voltage reference.

3. The voltage detector of claim 1 further comprising:

a first voltage control transistor (228) having a source to drain path coupling the source to drain path of the third transistor (206) of the third current mirror to the fifth node (n13) and having a gate coupled to V_DD ;

a second voltage control transistor (218) having a source to drain path coupling the source to drain path of the second transistor (204) of the third current mirror to the second node (n14) and having a gate coupled to V_DD ;

a third voltage control transistor (220) having a source to drain path coupling the source to drain path of the second transistor (221) of the fourth current mirror to the fourth node (n11), and having a gate coupled to V_DD ; and

a fourth voltage control transistor (226) having a source to drain path coupling the source to drain path of the first transistor (230) of the fourth current mirror to the sixth node (n12), and having a gate coupled to V_DD.

4. The voltage detector of claim 3 further comprising:

a fifth voltage control transistor (216) having a source to drain path coupling the source to drain path of the third voltage control transistor (220) to the fourth node (nil), and having a gate coupled to a fourth voltage potential (V₄) line; and

a sixth voltage control transistor (224) having a source to drain path coupling the source to drain path of the fourth voltage control transistor (226) to the sixth node (n12), and having a gate coupled to the fourth voltage potential (V₄) line.

5. The voltage detector of claim 1 further comprising:

two series connected inverters connected to the first end of the source to drain path of the second transistor (221) of the third current mirror to provide buffering of the output signal for the voltage detector circuit.

6. The voltage detector of claim 1 further comprising a comparator and inverter (240) to provide buffering of the output signal for the voltage detector circuit, the comparator comprising:

a first current sink transistor (234) having a source to drain with a first end coupled to an input of the inverter (240) and a second end coupled to V_SS, and having a gate coupled to the first end of the source to drain path of the second transistor (221) of the third current mirror;

a second current sink transistor (236) having a source to drain path with a first end coupled to V_SS, and having a gate coupled to the first end of the source to drain path of the first transistor (230) of the third current mirror; and

a current mirror comprising;

a first transistor (232) having a source to drain path coupling V_DD to a second end of the source to drain path of the second current sink transistor (236), and having a gate coupled to the second end of the source to drain path of the second current sink transistor (236); and

a second transistor (231) having a source to drain path coupling V_DD to the input of the inverter (240), and having a gate coupled to the second end of the source to drain path of the second current sink transistor (236).

7. The voltage detector circuit of claim 1, wherein the first transistor (208) has a gate coupled to the first voltage potential (V₂) line.

8. A voltage detector circuit comprising:

a first NMOS transistor (208) having a source to drain path coupling a first voltage potential (V₂) line to a first node (n10);

a first PMOS transistor (200) having a source to drain path coupling a second voltage potential (V₁) line to a second node (n21), and having a gate connected to a third voltage potential (V₃) line;

a first current mirror comprising;

a first PMOS transistor (210) having a source to drain path coupled on a first end to the first node (n10) and on a second end to a third node (n14), and having a gate coupled to the third node (n14); and

a second PMOS transistor (214) having a source to drain path coupled on a first end to the second voltage potential (V₁) line and on a second end to a fourth node (n11), and having a gate coupled to the gate of the first PMOS transistor (210) of the first current mirror;

a second current mirror comprising;

a first PMOS transistor (212) having a source to drain path coupled on a first end to the second voltage potential (V₁) line and on a second end to a fifth node (n13), and having a gate coupled to the fifth node (n13); and

a second PMOS transistor (222) having a source to drain path coupled on a first end to the second voltage potential (V₁) line and on a second end to a sixth node (n12), and having a gate coupled to the gate of the first PMOS transistor (212) of the second current mirror;

a third current mirror comprising;

a first NMOS transistor (202) having a source to drain path coupling the second node (n21) to V_SS, and having a gate coupled to the second node (n21);

a second NMOS transistor (204) having a source to drain path coupling the third node (n14) to V_SS, and having a gate coupled to the second node (n21); and

a third NMOS transistor (206) having a source to drain path coupling the fifth node (n13) to V_SS, and having a gate coupled to the second node (n21); and

a fourth current mirror comprising;

a first PMOS transistor (230) having a source to drain path with a first end coupled to the sixth node (n12) and a second end coupled to V_SS, and having a gate coupled to the first end of its source to drain path; and

a second PMOS transistor (221) having a source to drain path with a first end coupled to the fourth node (nil) and a second end coupled to V_SS, and having a gate coupled to the gate of the first PMOS transistor (230) of the fourth current mirror, the first end of the source to drain path of the second PMOS transistor (221) for providing an output signal for the voltage detector circuit indicating if a voltage potential at the first node (n10) is greater or less than the second voltage potential (V₁) on the second voltage potential line.

9. The voltage detector of claim 8 further comprising:

a first NMOS voltage control transistor (228) having a source to drain path coupling the source to drain path of the third NMOS transistor (206) of the third current mirror to the fifth node (n13) and having a gate coupled to V_DD ;

a second NMOS voltage control transistor (218) having a source to drain path coupling the source to drain path of the second NMOS transistor (204) of the third current mirror to the second node (n14) and having a gate coupled to V_DD ;

a third NMOS voltage control transistor (220) having a source to drain path coupling the source to drain path of the second NMOS transistor (221) of the fourth current mirror at a seventh node (n20) to the fourth node (n11), and having a gate coupled to V_DD ; and

a fourth NMOS voltage control transistor (226) having a source to drain path coupling the source to drain path of the first NMOS transistor (230) of the fourth current mirror at an eighth node (n19) to the sixth node (n12), and having a gate coupled to V_DD.

10. The voltage detector of claim 9 further comprising:

a first PMOS voltage control transistor (216) having a source to drain path coupling the source to drain path of the third NMOS voltage control transistor (220) to the fourth node (n11), and having a gate coupled to a fourth voltage potential (V₄) line; and

a second PMOS voltage control transistor (224) having a source to drain path coupling the source to drain path of the fourth NMOS voltage control transistor (226) to the sixth node (n12), and having a gate coupled to the fourth voltage potential (V₄) line.

11. The voltage detector of claim 9 further comprising:

an inverter (240);

a first NMOS current sink transistor (234) having a source to drain with a first end coupled to an input of the inverter (240) and a second end coupled to V_SS, and having a gate coupled to the seventh node (n20);

a second NMOS current sink transistor (236) having a source to drain path with a first end coupled to V_SS, and having a gate coupled to the eighth node (n19); and

a fifth current mirror comprising;

a first PMOS transistor (232) having a source to drain path coupling V_DD to a second end of the source to drain path of the second NMOS current sink transistor (236), and having a gate coupled to the second end of the source to drain path of the second NMOS current sink transistor (236); and

a second PMOS transistor (231) having a source to drain path coupling V_DD to the input of the inverter (240), and having a gate coupled to the second end of the source to drain path of the second NMOS current sink transistor (236).