Low-noise frequency divider

• US 6,163,182 A
• Filed: 04/14/1998
• Issued: 12/19/2000
• Est. Priority Date: 04/15/1997
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Fillatre, Vincent, Canard, David
• Primary Examiner(s): LAM, TUAN THIEU
• Application Number:
  US09/060,089
• Time in Patent Office: 980 Days
• Field of Search: 327/115, 327/117, 327/118, 377/47, 377/48
• US Class Current: 327/117
• CPC Class Codes: H03J 5/0272 the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
• CPC Class Codes: H03K 23/542 with crossed-couplings, i.e. Johnson counters

Abstract

A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.

Claims

1. An integrated circuit comprising a programmable frequency divider having a first input for receiving a signal having an input frequency, a second input for receiving a control signal, and an output, the programmable frequency divider comprising:

a first frequency divider having an input constituting the input of the programmable frequency divider, and an output for supplying a signal having an intermediate frequency whose value is 2.P times lower than that of the input frequency, in which P is a predetermined integer,

a second frequency divider having an input connected to the output of the first frequency divider, and an output constituting the output of the programmable frequency divider for supplying a signal having an output frequency whose value is K times lower than that of the intermediate frequency, in which K is a real number whose value is determined by the value of the control signal,

characterized in that, with P being higher than or equal to N, the first frequency divider comprises a frequency divider circuit having a symmetrical input for receiving a signal having a first frequency, and a symmetrical output for providing a signal having a second frequency whose value is 2.N times lower than that of the first frequency, in which N is a predetermined integer which is at least equal to 2, the frequency divider being composed of memory cells realized in ECL technology, each having a symmetrical data input, a symmetrical clock input and a symmetrical data output, characterized in that the frequency divider comprises 2.N memory cells of the above-mentioned type, the data output of the i^th memory cell, referred to as memory cell of rank i, being connected, for i=1 to 2.N-1, to the data input of the memory cell of rank i+1, the data output of the memory cell of rank 2.N being cross-connected to the data input of the memory cell of rank 1, the data output of one of the memory cells constituting the output of the frequency divider circuit, the clock input of each memory cell of an odd rank being connected to the symmetrical input of the frequency divider circuit, the clock input of each memory cell of an even rank being cross-connected to said symmetrical input.

2. A selection device having a signal input for receiving a radio-electric signal, a second control input for receiving a control signal defining the frequency of a radio-electric signal to be selected, and an output, said device comprising:

an oscillator having a tuning input and an output for supplying a signal whose frequency depends on the value of a signal applied to its tuning input,

a mixer having a first input constituting the signal input of the device, a second input connected to the output of the oscillator, and an output constituting the output of the device for supplying a signal whose frequency is equal to the difference between the frequency of the signal received at its first input and that of the signal received at its second input,

a programmable frequency divider having a first input connected to the output of the oscillator, a second input constituting the control input of the device, and an output for supplying a signal whose frequency is defined by the value of the control signal,

a phase detector having a first input for receiving a reference signal whose frequency is fixed, a second input connected to the output of the programmable frequency divider, and an output connected to the tuning input of the oscillator, and provided with means for supplying, at its output, a signal whose value depends on the difference between the phases of its input signals,

said device being characterized in that the programmable frequency divider has having a first input for receiving a signal having an input frequency, a second input for receiving said control signal, and an output, the programmable frequency divider comprising;

a first frequency divider having an input constituting the input of the programmable frequency divider, and an output for supplying a signal having an intermediate frequency whose value is 2.P times lower than that of the input frequency, in which P is a predetermined integer,

a second frequency divider having an input connected to the output of the first frequency divider, and an output constituting the output of the programmable frequency divider for supplying a signal having an output frequency whose value is K times lower than that of the intermediate frequency, in which K is a real number whose value is determined by the value of the control signal,

characterized in that, with P being higher than or equal to N, the first frequency divider comprises a frequency divider circuit having a symmetrical input for receiving a signal having a first frequency, and a symmetrical output for providing a signal having a second frequency whose value is 2.N times lower than that of the first frequency, in which N is a predetermined integer which is at least equal to 2, the frequency divider being composed of memory cells realized in ECL technology, each having a symmetrical data input, a symmetrical clock input and a symmetrical data output, characterized in that the frequency divider comprises 2.N memory cells of the above-mentioned type, the data output of the i^th memory cell, referred to as memory cell of rank i, being connected, for i=1 to 2.N-1, to the data input of the memory cell of rank i+1, the data output of the memory cell of rank 2.N being cross-connected to the data input of the memory cell of rank 1, the data output of one of the memory cells constituting the output of the frequency divider circuit, the clock input of each memory cell of an odd rank being connected to the symmetrical input of the frequency divider circuit, the clock input of each memory cell of an even rank being cross-connected to said symmetrical input.