Bit line cross-over layout arrangement

• US 6,163,475 A
• Filed: 04/01/1999
• Issued: 12/19/2000
• Est. Priority Date: 02/13/1999
• Status: Expired due to Term

• Current Assignee: InnoMemory, LLC (Jeffrey M. Gross)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/285,232
• Time in Patent Office: 628 Days
• Field of Search: 365/69, 365/51, 365/63, 365/72
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 2207/229 Timing of a write operation
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A novel crossover arrangement reduces the area of a memory array by using only one crossover structure within each array block. Yet the total differential signal degradation for each respective true and complement bit line pair arising from coupling between the respective true bit line and the respective complement bit line as well as differential coupling to the respective true and complement bit lines from unrelated adjacent true or complement bit lines, is no worse than that resulting from a true bit line being adjacent to its complement bit line for their entire length. For one embodiment of the invention, each complementary pair of bit lines runs vertically within an array block from the top to the bottom of the array block. The true bit line and complement bit line of a first pair run adjacent to each other from the top to the bottom of the array block without any crossovers. The true bit line and complement bit line of a second pair do not run adjacent to each other, but instead straddle the first pair (i.e., both true and complement bit lines of the first pair lie between the true and complement bit lines of the second pair), with a single crossover half-way down the second bit line pair (vertically in the middle of the array block). This crossover arrangement repeats horizontally throughout each array block in groups of two pairs of bit lines (four physical bit line wires). By using this crossover arrangement, if guard cells are used only four groups of guard cells are needed in each array block-one each at the top and bottom of the array block, and one each at the top and bottom of the single crossover structure located preferably at the vertical center of the array block.

Claims

1. In an integrated circuit, a memory array comprising:

a first plurality of complementary bit line pairs vertically traversing across an array block, each pair comprising a first true bit line disposed adjacent to a first complement bit line; and

a second plurality of complementary bit line pairs vertically traversing across the array block, each pair comprising

a second true bit line and a second complement bit line disposed within the array block on opposite sides of a respective pair of the first plurality of complementary bit line pairs; and

a crossover structure disposed approximately half-way across the array block, wherein at the crossover structure the second true bit line and the second complement bit line interchange sides.

2. A memory array as in claim 1 wherein each of the first plurality of complementary bit line pairs vertically traverses across the array block utilizing no crossover structures.

3. A memory array as in claim 1 further comprising:

at least one row of guard cells disposed between the respective crossover structures and addressable rows of memory cells located above the respective crossover structures; and

at least one row of guard cells disposed between the respective crossover structures and addressable rows of memory cells located below the respective crossover structures.

5. A memory array as in claim 1 wherein the memory array comprises a dynamic memory array.

40. A memory array as in claim 1 wherein:

each of the first plurality of complementary bit line pairs is associated with a respective plurality of memory cells which is not associated with any of the second plurality of complementary bit line pairs; and

each of the second plurality of complementary bit line pairs is associated with a respective plurality of memory cells which is not associated with any of the first plurality of complementary bit line pairs.

41. A memory array as in claim 1 wherein:

each true and complement bit line of the first plurality of complementary bit line pairs and each true and complement bit line of the second plurality of complementary bit line pairs are substantially implemented in a given interconnect layer.

4. In an integrated circuit, a memory array comprising:

a first plurality of complementary bit line pairs vertically traversing across an array block, each pair comprising a first true bit line disposed adjacent to a first complement bit line;

a second plurality of complementary bit line pairs vertically traversing across the array block, each pair comprising

a second true bit line and a second complement bit line disposed within the array block on opposite sides of a respective pair of the first plurality of complementary bit line pairs; and

a crossover structure disposed approximately half-way across the array block, wherein at the crossover structure the second true bit line and the second complement bit line interchange sides;

a first plurality of bit line sense amplifiers, each respectively coupled to a respective one of the first plurality of complementary bit line pairs and disposed at one end of the complementary bit line pairs; and

a second plurality of bit line sense amplifiers, each respectively coupled to a respective one of the second plurality of complementary bit line pairs and disposed at the other end of the complementary bit line pairs.

6. In an integrated circuit, a memory array comprising:

a first pair of complementary bit lines comprising a first true bit line and a first complement bit line together vertically traversing at least a certain distance across the memory array, said first true bit line disposed adjacent to said first complement bit line; and

a second pair of complementary bit lines comprising

a second true bit line and a second complement bit line vertically traversing at least the certain distance across the memory array and horizontally straddling the first pair of complementary bit lines, whereby both the first true bit line and the first complement bit line are disposed between the second true bit line and the second complement bit line for substantially the certain distance; and

a first crossover structure disposed at a position along the second pair of complementary bit lines corresponding to a first portion of the certain distance;

wherein the second true bit line traverses across the memory array for the first portion of the certain distance disposed on a first side of the first pair of bit lines, then crosses over the first pair of bit lines at the first crossover structure and continues for a remaining portion of the certain distance disposed on a second side of the first pair of bit lines opposite the first side; and

wherein the second complement bit line traverses across the memory array for the first portion of the certain distance disposed to the second side of the first pair of bit lines, then crosses over the first pair of bit lines and crosses over the second true bit line at the first crossover structure and continues for the remaining portion of the certain distance disposed to the first side of the first pair of bit lines.

7. A memory array as in claim 6 wherein the first pair of complementary bit lines vertically traverse across the certain distance utilizing no crossover structure.

8. A memory array as in claim 6 wherein the certain distance comprises substantially a total length of the first and second pairs of complementary bit lines.

9. A memory array as in claim 8 wherein the certain distance further comprises substantially a total height of an array block of the memory array.

10. A memory array as in claim 6 wherein the certain distance comprises but a portion of a total length of the first and second pairs of complementary bit lines.

11. A memory array as in claim 6 further comprising:

at least one row of guard cells disposed between the first crossover structure and addressable rows of memory cells located above the first crossover structure; and

at least one row of guard cells disposed between the first crossover structure and addressable rows of memory cells located below the first crossover structure.

12. A memory array as in claim 6 wherein the first portion of the certain distance and the remaining portion of the certain distance are substantially equal.

13. A memory array as in claim 6 wherein the each of the first pair of complementary bit lines and each of the second pair of complementary bit lines are substantially implemented in a given interconnect layer.

14. A memory array as in claim 6 further comprising:

a first bit line sense amplifier coupled to the first pair of complementary bit lines and disposed at one end of the first and second pairs of complementary bit lines; and

a second bit line sense amplifier coupled to the second pair of complementary bit lines and disposed at the other end of the first and second pairs of complementary bit lines.

15. A memory array as in claim 6 further comprising:

a third pair of complementary bit lines comprising a third true bit line and a third complement bit line together vertically traversing at least the certain distance across the memory array, said third true bit line disposed adjacent to said third complement bit line; and

a fourth pair of complementary bit lines comprising

a fourth true bit line and a fourth complement bit line vertically traversing at least the certain distance across the memory array and horizontally straddling the third pair of complementary bit lines, whereby both the third true bit line and the third complement bit line are disposed between the fourth true bit line and the fourth complement bit line for substantially the certain distance; and

a second crossover structure disposed at a position along the fourth pair of complementary bit lines corresponding to the first portion of the certain distance;

wherein the fourth true bit line traverses across the memory array for the first portion of the certain distance disposed on a first side of the third pair of bit lines, then crosses over the third pair of bit lines at the second crossover structure and continues for the remaining portion of the certain distance disposed on a second side of the third pair of bit lines opposite the first side;

wherein the fourth complement bit line traverses across the memory array for the first portion of the certain distance disposed to the second side of the third pair of bit lines, then crosses over the third pair of bit lines and crosses over the fourth true bit line at the second crossover structure and continues for the remaining portion of the certain distance disposed to the first side of the third pair of bit lines; and

wherein a group comprising the third and fourth pair of complementary bit lines is disposed adjacent to a group comprising the first and second pair of complementary bit lines.

16. A memory array as in claim 15 wherein each bit line of the first, second, third and fourth pairs of complementary bit lines is horizontally spaced uniformly to its respective two adjacent bit lines, both above and below the first and second crossover structures.

17. A memory array as in claim 13 wherein the crossover structure is implemented in interconnect layers other than the given interconnect layer.

18. A memory array as in claim 17 wherein the given interconnect layer comprises a polysilicon interconnect layer, and wherein the first crossover structure is implemented using at least one metal interconnect layer.

19. A memory array as in claim 18 wherein the polysilicon interconnect layer comprises a silicided polysilicon layer.

20. A memory array as in claim 6 incorporated into an integrated circuit including a processor.

21. A memory array as in claim 6 wherein the memory array comprises a plurality of memory cells, each of which connects to only one of either a true bit line or a complement bit line.

22. A memory array as in claim 21 wherein the memory array comprises a dynamic memory array.

23. A memory array as in claim 21 wherein the memory array comprises a read-only memory array.

24. A memory array as in claim 21 wherein the memory array comprises a programmable read-only memory array.

42. A memory array as in claim 6 wherein:

the first pair of complementary bit lines is associated with a first plurality of memory cells which is not associated with the second pair of complementary bit lines; and

the second pair of complementary bit lines is associated with a second plurality of memory cells which is not associated with the first pair of complementary bit lines.

43. A memory array as in claim 6 wherein:

the second pair of complementary bit lines includes only one crossover structure.

44. A memory array as in claim 6 further comprising:

a first plurality of memory cells associated with the first pair of complementary bit lines and not associated with the second pair of complementary bit lines;

a second plurality of memory cells associated with the second pair of complementary bit lines and not associated with the first pair of complementary bit lines;

a first bit line sense amplifier coupled to the first pair of complementary bit lines and disposed at one end of the first and second pairs of complementary bit lines; and

a second bit line sense amplifier coupled to the second pair of complementary bit lines and disposed at the other end of the first and second pairs of complementary bit lines.

45. A memory array as in claim 44 wherein:

each of the true and complement bit lines of the first pair of complementary bit lines and the true and complement bit lines of the second pair of complementary bit lines is substantially implemented in a given interconnect layer, and is horizontally spaced uniformly to its adjacent bit lines, both above and below the first crossover structure.

25. In an integrated circuit, a dynamic memory array comprising:

a first pair of complementary bit lines comprising a first true bit line and a first complement bit line together vertically traversing across an array block without crossovers, each of said first pair of complementary bit lines fabricated substantially from a given interconnect level and disposed substantially adjacent to, parallel to, and at a certain spacing from the other; and

a second pair of complementary bit lines comprising

a second true bit line and a second complement bit line fabricated substantially from the given interconnect level, said second true and second complement bit lines vertically traversing across the array block horizontally straddling the first pair of bit lines, whereby both the first true bit line and the first complement bit line are disposed between the second true bit line and the second complement bit line; and

a first crossover structure vertically disposed at a position along the second pair of complementary bit lines approximately half-way across the array block;

wherein the second true bit line traverses across the upper half of the array block disposed at the certain spacing from a first side of the first pair of bit lines, then crosses over the first pair of bit lines at the first crossover structure and traverses across the lower half of the array block disposed at the certain spacing from a second side of the first pair of bit lines opposite the first side; and

wherein the second complement bit line traverses across the upper half of the array block disposed at the certain spacing from the second side of the first pair of bit lines, then crosses over the first pair of bit lines and crosses over the second true bit line at the first crossover structure and traverses across the lower half of the array block disposed at the certain spacing from the first side of the first pair of bit lines.

26. A memory array as in claim 25 further comprising:

at least one row of guard cells between the first crossover structure and addressable memory cells located above the first crossover structure; and

at least one row of guard cells disposed between the first crossover structure and addressable memory cells located below the first crossover structure.

27. A memory array as in claim 25 further comprising:

a first bit line sense amplifier coupled to the first pair of complementary bit lines and disposed at one end of the first and second pairs of complementary bit lines; and

a second bit line sense amplifier coupled to the second pair of complementary bit lines and disposed at the other end of the first and second pairs of complementary bit lines.

28. A memory array as in claim 25 wherein the given interconnect layer comprises a silicided polysilicon interconnect layer, and wherein the first crossover structure is implemented using at least one metal interconnect layer.

46. A memory array as in claim 25 wherein:

the first pair of complementary bit lines is associated with a first plurality of memory cells which is not associated with the second pair of complementary bit lines; and

the second pair of complementary bit lines is associated with a second plurality of memory cells which is not associated with the first pair of complementary bit lines.

29. In a memory array having a plurality of complementary bit line pairs, a method of reducing layout area of the memory array while affording, for each respective true and complement bit line pair, a total differential signal degradation, arising from coupling between the respective true bit line and the respective complement bit line as well as differential coupling to the respective true and complement bit lines from unrelated adjacent true or complement bit lines, which is no worse than that resulting from a true bit line being adjacent to its complement bit line for their entire length, said method comprising:

providing a first plurality of complementary bit line pairs vertically traversing across an array block, each pair comprising a first true bit line disposed adjacent to a first complement bit line; and

providing a second plurality of complementary bit line pairs vertically traversing across the array block, each pair comprising

a second true bit line and a second complement bit line disposed within the array block on opposite sides of a respective pair of the first plurality of complementary bit line pairs; and

a crossover structure disposed approximately half-way across the array block, wherein at the crossover structure the second true bit line and the second complement bit line interchange sides;

said total differential signal degradation being afforded using only a single row of said crossover structures.

30. A method as in claim 29 wherein each of the first plurality of complementary bit line pairs vertically traverse across the array block utilizing no crossover structures.

31. A method as in claim 29 wherein the memory array comprises a plurality of memory cells, each of which connects to only one of either a true bit line or a complement bit line.

32. A method as in claim 31 wherein the memory array comprises a dynamic memory array.

33. A method as in claim 31 wherein the memory array comprises a read-only memory array.

34. A method as in claim 31 wherein the memory array comprises a programmable read-only memory array.

35. A method as in claim 29 employed in a dynamic memory array embedded within an integrated processor circuit.

47. A method as in claim 29 further comprising:

providing for each of the first plurality of complementary bit line pairs an associated respective plurality of memory cells which is not associated with any of the second plurality of complementary bit line pairs; and

providing for each of the second plurality of complementary bit line pairs an associated respective plurality of memory cells which is not associated with any of the first plurality of complementary bit line pairs.

48. A method as in claim 29 further comprising:

providing a first plurality of bit line sense amplifiers, each respectively coupled to a respective one of the first plurality of complementary bit line pairs and disposed at one end of the complementary bit line pairs; and

providing a second plurality of bit line sense amplifiers, each respectively coupled to a respective one of the second plurality of complementary bit line pairs and disposed at the other end of the complementary bit line pairs.

49. A method as in claim 29 further comprising:

implementing each true and complement bit line of the first plurality of complementary bit line pairs and each true and complement bit line of the second plurality of complementary bit line pairs in a given interconnect layer.

36. In an integrated circuit, a memory array comprising:

a first complementary bit line pair comprising a first true bit line and a first complement bit line;

a second bit line generally disposed between the first true bit line and the first complement bit line; and

a third bit line adjacent to the second bit line and also generally disposed between the first true bit line and the first complement bit line;

wherein the second and third bit lines together comprise a second complementary bit line pair; and

wherein the first complementary bit line pair is associated with a first plurality of memory cells and the second complementary bit line pair is associated with a second plurality of memory cells different from the first plurality of memory cells.

37. A memory array as in claim 36 further comprising:

a crossover structure for the first complementary bit line pair, wherein at the crossover structure the first true bit line and the first complement bit line interchange sides of the second complementary bit line air disposed therebetween.

38. A memory array as in claim 36 wherein each of the memory cells associated with a respective complementary bit line pair connects to only one of either a true bit line or a complement bit line of the respective complementary bit line pair.

39. A memory array as in claim 38 wherein the memory array comprises a dynamic memory array.

50. A memory array as in claim 36 further comprising:

a first bit line sense amplifier coupled to the first complementary bit line pair and disposed at one end of the complementary bit line pairs; and

a second bit line sense amplifier coupled to the second complementary bit line pair and disposed at the other end of the complementary bit line pairs.

51. A memory array as in claim 36 wherein:

the first true and first complement bit lines of the first complementary bit line pair, and the second bit line and third bit line forming the second complementary bit line pair are each substantially implemented in a given interconnect layer.

52. In an integrated circuit, a memory array comprising:

a first plurality of complementary bit line pairs vertically traversing across an array block, each pair coupled to a respective one of a first plurality of bit line sense amplifiers, and each pair comprising a first true bit line disposed adjacent to a first complement bit line; and

a second plurality of complementary bit line pairs vertically traversing across the array block, each pair coupled to a respective one of a second plurality of bit line sense amplifiers, and each pair comprising

a second true bit line and a second complement bit line disposed within the array block on opposite sides of a respective pair of the first plurality of complementary bit line pairs; and

a crossover structure disposed approximately half-way across the array block, wherein at the crossover structure the second true bit line and the second complement bit line interchange sides.

53. In an integrated circuit, a memory array comprising:

a first pair of complementary bit lines comprising a first true bit line and a first complement bit line together vertically traversing at least a certain distance across the memory array, said first true bit line disposed adjacent to said first complement bit line; and

a second pair of complementary bit lines comprising

a second true bit line and a second complement bit line vertically traversing at least the certain distance across the memory array and horizontally straddling the first pair of complementary bit lines, whereby both the first true bit line and the first complement bit line are disposed between the second true bit line and the second complement bit line for substantially the certain distance; and

a first crossover structure disposed at a position along the second pair of complementary bit lines corresponding to a first portion of the certain distance;

wherein one of the second true and complement bit lines traverses across the memory array for the first portion of the certain distance disposed on a first side of the first pair of bit lines, then crosses the first pair of bit lines at the first crossover structure and continues for a remaining portion of the certain distance disposed on a second side of the first pair of bit lines opposite the first side; and

wherein the other of the second true and complement bit lines traverses across the memory array for the first portion of the certain distance disposed to the second side of the first pair of bit lines, then crosses the first pair of bit lines and said one of the second true and complement bit lines at the first crossover structure and continues for the remaining portion of the certain distance disposed to the first side of the first pair of bit lines.