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Synchronous semiconductor memory device

  • US 6,163,501 A
  • Filed: 03/08/2000
  • Issued: 12/19/2000
  • Est. Priority Date: 03/08/1999
  • Status: Expired due to Fees
First Claim
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1. A synchronous semiconductor memory device comprising:

  • a memory cell array;

    a decoder circuit for decoding an address which is supplied in synchronism with a clock, to select a memory cell of said memory cell array;

    a plurality of main data line pairs to which data of said memory cell array are transferred;

    a plurality of data line buffers each of which is provided in a corresponding one of said main data line pairs and each of which includes a latch circuit; and

    a plurality of peripheral data lines for transferring data of each of said data line buffers to a data input/output terminal,wherein a plurality of bits of data per data input/output terminal read out in parallel from said memory cell array, as a pre-fetch read out operation, are transferred to said data line buffers via said main data line pairs in parallel during one cycle of said clock, control signals each corresponding to each of plurality of bits of data are generated based on specific one or more bits of said address, said control signals are applied to said data line buffers, and while head data of said plurality of bits of data transfer from said latch circuits to one of said peripheral data lines, a plurality of continuous data are temporarily held in said latch circuits, and subsequent data are sequentially transferred by said control signals to the same peripheral data line as said one of said peripheral data lines, to which the head data have been transferred.

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