Synchronous semiconductor memory device

• US 6,163,501 A
• Filed: 03/08/2000
• Issued: 12/19/2000
• Est. Priority Date: 03/08/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ozawa, Susumu, Ohshima, Shigeo
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/520,720
• Time in Patent Office: 286 Days
• Field of Search: 365/233, 365/189.05, 365/220, 365/239
• US Class Current: 365/189.05
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A synchronous semiconductor memory device comprises: a memory cell array; a decoder circuit for decoding an address, which is supplied in synchronism with a clock, to select a memory cell of the memory cell array; a plurality of main data line pairs, to which data of the memory cell array are transferred; a plurality of data line buffers, each of which is provided in a corresponding one of the main data line pairs and each of which includes a latch circuit; and a plurality of peripheral data lines for transferring data of each of the data line buffers to a data input/output terminal, wherein a plurality of bits of data per data input/output terminal read out of the memory cell array are transferred to the data line buffers via the main data line pairs in parallel, and while head data of the plurality of bits of data pass through the latch circuits to be transferred to one of the peripheral data lines, a plurality of continuous data are temporarily held by the latch circuit, and subsequent data are sequentially transferred to the same peripheral data line as the one of the peripheral data lines, to which the head data have been transferred. Thus, it is possible to decrease the number of peripheral data lines to reduce the chip size of an SDRAM while adopting a pre-fetch system for accelerating a data transfer cycle.

Claims

1. A synchronous semiconductor memory device comprising:

a memory cell array;

a decoder circuit for decoding an address which is supplied in synchronism with a clock, to select a memory cell of said memory cell array;

a plurality of main data line pairs to which data of said memory cell array are transferred;

a plurality of data line buffers each of which is provided in a corresponding one of said main data line pairs and each of which includes a latch circuit; and

a plurality of peripheral data lines for transferring data of each of said data line buffers to a data input/output terminal,

wherein a plurality of bits of data per data input/output terminal read out in parallel from said memory cell array, as a pre-fetch read out operation, are transferred to said data line buffers via said main data line pairs in parallel during one cycle of said clock, control signals each corresponding to each of plurality of bits of data are generated based on specific one or more bits of said address, said control signals are applied to said data line buffers, and while head data of said plurality of bits of data transfer from said latch circuits to one of said peripheral data lines, a plurality of continuous data are temporarily held in said latch circuits, and subsequent data are sequentially transferred by said control signals to the same peripheral data line as said one of said peripheral data lines, to which the head data have been transferred.

2. A synchronous semiconductor memory device as set forth in claim 1, wherein each of said data line buffers has a data line sense amplifier which is operated by an activating signal, the timing of which being controlled by said clock, and said latch circuit is connected to said data line sense amplifier to be operated by said activating signal as a latch signal.

3. A synchronous semiconductor memory device as set forth in claim 2, wherein each said latch circuit includes a latch circuit main portion being operated by said activating signal of said data line sense amplifier as said latch signal, and a driver for transferring a data stored in said latch circuit main portion to said peripheral data line, data output operation of said driver is controlled by said control signal.

4. A synchronous semiconductor memory device as set forth in claim 1, wherein each of said peripheral data lines has the construction of a single solid wire per 1-bit data, and a plurality of bits of data per one data input/output terminal are transferred to said data line buffers in parallel, said plurality of bits of data being transferred to one of said peripheral data lines in a time shearing operation.

5. A synchronous semiconductor memory device as set forth in claim 1, wherein each of said peripheral data lines has the construction of a pair of complementary signal lines per 1-bit data, and a plurality of bits of data per one data input/output terminal are transferred to said data line buffers in parallel, said plurality of bits of data being transferred to one pair of said peripheral data lines in a time shearing operation.

6. A synchronous semiconductor device as set forth in claim 1, wherein said plurality of bits of data pre-fetched are two bits, and said specific one or more bits of said address is the least significant bit.

7. A synchronous semiconductor device as set forth in claim 1, wherein said plurality of bits of data pre-fetched are four bits, and said specific one or more bits of said address are the least significant bit and the adjacent bit thereof.

8. A synchronous semiconductor device as set forth in claim 1, wherein said plurality of bits of data pre-fetched are 2ⁿ (n:

integer number over one) bits, and said specific one or more bits of said address are n column address bits of the least significant bit and the adjacent bit thereof.

9. A synchronous semiconductor memory device comprising:

a memory cell array including a plurality of bit lines and a plurality of word lines provided so as to intersect said plurality of bit lines, and a plurality of dynamic memory cells each of which being arranged at a corresponding one of the intersections between said plurality of word lines and said plurality of word lines;

a decoder circuit for decoding an address which is supplied in synchronism with a clock, to select one of said bit lines and one of said word lines of said memory cell array;

a plurality of main data line pairs, to which pairs a plurality of bits of data per data input/output terminals, being selected and transferred in parallel from said memory cell array by said decorder circuit;

a plurality of data line buffers each of which is provided in a corresponding one of said main data line pairs, each of said plurality of data line buffers being timing-controlled so as to sense said plurality of bits of data, which data being transferred in parallel in one cycle of said clock, to output the sensed data in a time shearing operation in serial by adding control signals to said data line buffer, each of said control signals corresponding to each of plurality of bits of data, which control signals being generated based on specific one or more bits of said address; and

a plurality of peripheral data lines for serially transferring a plurality of bits of data, which are outputted in serial from said data line buffers in the time shearing operation, to a common data input/output terminal.

10. A synchronous semiconductor memory device as set forth in claim 9, wherein each of said data line buffers has a data line sense amplifier and a latch circuit, said data line sense amplifier being operated by an activating signal produced in synchronism with said clock, said latch circuit being connected to said data line sense amplifier for being operated by said activating signal as a latch signal.

11. A synchronous semiconductor memory device as set forth in claim 10, wherein each said latch circuit includes a latch circuit main portion being operated by said activating signal of said data line sense amplifier as said latch signal, and a driver for transferring a data stored in said latch circuit main portion to said peripheral data line, data output operation of said driver is controlled by said control signal.

12. A synchronous semiconductor memory device as set forth in claim 10, wherein each of said peripheral data lines has the construction of a single solid wire per 1-bit data, and a plurality of bits of data per one data input/output terminal are transferred to said data line buffers in parallel, said plurality of bits of data being transferred to one of said peripheral data lines in a time shearing operation.

13. A synchronous semiconductor memory device as set forth in claim 10, wherein each of said peripheral data lines has the construction of a pair of complementary signal lines per 1-bit data, and a plurality of bits of data per one data input/output terminal are transferred to said data line buffers in parallel, said plurality of bits of data being transferred to one pair of said peripheral data lines in a time shearing operation.

14. A synchronous semiconductor memory device comprising:

a memory core capable of pre-fetching a plurality of bits of data selected by an address;

a plurality of main data lines each of which outputs 1-bit data of said plurality of bits of data from said memory core;

a plurality of latches each of which is connected to a corresponding one of said main data lines; and

a peripheral data line which is connected to an output side of each of said plurality of latches and connected to an I/O terminal,

wherein said plurality of latches are arranged to sequentially output said plurality of bits of data in one cycle of clock to said peripheral data line based on specific one or more bits of said column address.

15. A synchronous semiconductor memory device as set forth in claim 14, wherein said plurality of bits of data pre-fetched are two bits, and said specific one or more bits of said column address is the least significant bit of said column address.

16. A synchronous semiconductor memory device as set forth in claim 14, wherein said plurality of bits of data pre-fetched are four bits, and said specific one or more bits are the least significant bit and the adjacent bit thereof.

17. A synchronous semiconductor memory device as set forth in claim 14, wherein plurality of bits of data pre-fetched are 2ⁿ (n:

integer number over one) bits, and said specific one or more bits of said address are n column address bits of the least significnat bit side.

18. A data transfer method in a synchronous semiconductor memory device, said method comprising the steps of:

giving an address to a memory core to pre-fetch a plurality of bits of data;

storing each of the pre-fetched plurality of bits of data in each of latches; and

sequentially opening each of said latches by each of control signals, each of said control signals corresponding to each of specific bits of column address, to serially output 1-bit data in one cycle of clock from each of said latches to a peripheral data line.

19. A data transfer method in a synchronous semiconductor memory device as set forth in claim 18, wherein said plurality of bits of data are two bits, and said specific one or more bits of said column address is the least significant bit of said column address.

20. A data transfer method in a synchronous semiconductor memory device as set forth in claim 18, wherein said plurality of bits of data are four bits, and said specific one or more bits are the least significant bit and the adjacent bit thereof.

21. A data transfer method in a synchronous semiconductor memory device as set forth in claim 18, wherein said plurality of bits of data pre-fetched are 2ⁿ (n:

integer number over one) bits, and said specific one or more bits of said address are n column address bits of the least significant bit side.