Dynamic clocking apparatus and system for reducing power dissipation

• US 6,163,583 A
• Filed: 03/25/1998
• Issued: 12/19/2000
• Est. Priority Date: 03/25/1998
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation Of America (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Lin, Kenneth C., Yu, Andrew W., Kurata, Takahiro
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Fan, Chieh M.
• Application Number:
  US09/048,132
• Time in Patent Office: 1,000 Days
• Field of Search: 375/354, 375/355, 375/356, 375/357, 375/376, 713/400, 713/500, 713/501, 713/600, 713/601, 713/322
• US Class Current: 375/354
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A dynamic clocking computer system for a processor. The dynamic clocking computer system comprises a clock divider circuit, a multiplexer, and a state machine circuit. The clock divider circuit receives a first clock and outputs the first clock and generates a second clock. The second clock is supplied to external circuitry. The state machine circuit is coupled to the clock divider circuit and receives the first and second clocks from the clock divider circuit. The state machine circuit also receives an external access signal indicating an internal clock to select from the first and second clocks. In response to the external access signal, the state machine circuit generates a select signal to enable the multiplexer to select an internal clock. When the selected internal clock is the second clock, the internal clock is synchronized to the second clock. The multiplexer is coupled to the clock divider circuit and receives the first and second clocks through the clock divider circuit. In response to the select signal generated by the state machine circuit, the multiplexer selects an internal clock from the first and second clocks. The internal clock is then provided to the processor. By thus providing a lower clock frequency to the processor for external access operations, the present invention reduces power dissipation.

Claims

1. A dynamic clocking apparatus comprising:

a clock divider circuit to receive a first clock and to generate a slower second clock and also to output the first clock;

a state machine circuit to receive the first and second clocks from the clock divider circuit, the state machine circuit receiving an external access signal indicating which clock between the first and second clocks to supply as an internal clock, the state machine circuit for generating a select signal for selecting the internal clock between the first and second clocks; and

a multiplexer coupled to the clock divider circuit for selecting the internal clock from the first and second clocks in response to the select signal and for synchronizing the internal clock with the second clock in response to the select signal when selecting the second clock, the internal clock is provided to the processor and wherein the external access signal selects the second clock as the internal clock during external memory access operations performed by the processor.

2. The apparatus as recited in claim 1 wherein the state machine circuit generates three states including:

a run state for selecting the first clock;

a hold state for selecting a ground signal for synchronizing the internal clock to the second clock when switching the internal clock from the first clock to the second clock; and

an external state for selecting the second clock.

3. The apparatus as recited in claim 2 wherein the multiplexer receives the ground signal as input for synchronizing the internal clock to the second clock when switching the internal clock from the first clock to the second clock during the hold state.

4. The apparatus as recited in claim 2 wherein the state machine circuit generates the hold state when transitioning from the run state to the external state.

5. The apparatus as recited in claim 2 wherein the state machine circuit maintains the hold state until the next rising edge of the second clock is encountered.

6. The apparatus as recited in claim 2 wherein the state machine circuit switches from the external state to the run state on the rising edge of the first clock.

7. The apparatus as recited in claim 1 further comprising a clock generator circuit coupled to the clock divider circuit, the clock generator circuit for generating the first clock.

8. A computer system having a processor, a bus, and a circuit for providing a clock to the processor, the circuit comprising:

clock divider circuit to receive a first clock, to generate a slower second clock and also to output the first clock;

state machine circuit for generating a select signal for selecting an internal clock between the first and second clocks, wherein the state machine circuit receives the first and second clocks from the clock divider circuit, further wherein the state machine circuit receives an external access signal indicating which clock between the first and second clocks to supply as the internal clock; and

multiplexer circuit for receiving the first and second clocks from the clock divider circuit, for selecting the internal clock from the first and second clocks in response to the select signal and for synchronizing the internal clock with the second clock in response to the select signal when selecting the second clock, the internal clock provided to the processor and wherein the external access signal selects the second clock as the internal clock during external memory access operations performed by the processor.

9. The computer system as recited in claim 8 further comprising a clock generator circuit, coupled to the clock divider circuit, for generating the first clock.

10. The computer system as recited in claim 8 wherein the state machine circuit is also for generating three states including:

a run state for selecting the first clock;

a hold state for selecting a ground signal for synchronizing the internal clock to the second clock when switching the internal clock from the first clock to the second clock; and

an external state for selecting the second clock.

11. The computer system as recited in claim 10 wherein the multiplexer circuit receives the ground signal as input for synchronizing the internal clock to the second clock when switching the internal clock from the first clock to the second clock during the hold state.

12. The computer system as recited in claim 10 wherein the state machine circuit is also for generating the hold state when transitioning from the run state to the external state.

13. The computer system as recited in claim 10 wherein the state machine circuit maintains the hold state until the next rising edge of the second clock is encountered.

14. The computer system as recited in claim 10 wherein the state machine circuit switches from the external state to the run state on the rising edge of the first clock.

15. In a computer system, a method for dynamically changing the clock speed of a processor, the method comprising the steps of:

a) receiving a first clock;

b) generating a slower second clock from the first clock and supplying the second clock to circuitry external to the processor;

c) asserting a selection signal during external memory access operations performed by the processor;

d) in response to the selection signal, selecting an internal clock between the first and second clocks;

e) synchronizing the internal clock with a transition of the second clock when step d) transitions from the first clock to the second clock; and

f) providing the internal clock to the processor.

16. The method as recited in claim 15 wherein said second clock is selected by step d) during said external memory access operations performed by said processor.

17. The method as recited in claim 16 wherein the selection signal is based on a bus request signal.

18. The method as recited in claim 16 wherein step e) further comprises the steps of:

holding the internal clock in an inactive state until a transition of the second clock; and

starting the clock cycle of the internal clock at the same time as the start of the clock cycle of the second clock.

19. The method as recited in claim 18 wherein the transition of the second clock is a rising edge.

20. The method as recited in claim 18 wherein the transition of the second clock is a falling edge.

21. A circuit for providing a clock to a processor, the circuit comprising:

a) means for receiving a first clock;

b) means for generating a slower second clock from the first clock and supplying the second clock to circuitry external to the processor;

c) means for asserting a selection signal during external memory access operations performed by the processor;

d) means for selecting an internal clock between the first and second clocks in response to the selection signal;

e) means for synchronizing the internal clock with a transition of the second clock when the means for selecting transitions from the first clock to the second clock; and

f) means for providing the internal clock to the processor.

22. The circuit as recited in claim 21 wherein said second clock is selected by the means for selecting during the external memory access operations performed by the processor.

23. The circuit as recited in claim 22 wherein the selection signal is based on a bus request signal.

24. The circuit as recited in claim 22 wherein the means for synchronizing further comprises:

means for holding the internal clock in an inactive state until a transition of the second clock; and

means for starting the clock cycle of the internal clock at the same time as the start of the clock cycle of the second clock.

25. The circuit as recited in claim 24 wherein the transition of the second clock is a rising edge.

26. The circuit as recited in claim 24 wherein the transition of the second clock is a falling edge.