Broadband frequency synthesizer

• US 6,163,684 A
• Filed: 08/01/1997
• Issued: 12/19/2000
• Est. Priority Date: 08/01/1997
• Status: Expired due to Term

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Microtune, Inc. (Qualcomm, Inc.)
• Inventors: Birleson, Vince
• Primary Examiner(s): Hunter, Daniel S.
• Assistant Examiner(s): Armstrong, Darnell R.
• Application Number:
  US08/904,907
• Time in Patent Office: 1,236 Days
• Field of Search: 455/173, 455/176.1, 455/178.1, 455/180.3, 455/182.1, 455/182.3, 455/183.1, 455/189.1, 455/190.1, 455/192.3, 375/376, 375/334
• US Class Current: 455/182.3
• CPC Class Codes: H03D 7/163 the local oscillations of at least two of the frequency changers being derived from a single oscillator
• CPC Class Codes: H03L 2207/14 Preventing false-lock or pseudo-lock of the PLL
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/12 using a scanning signal
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

A broadband frequency synthesizer including a first local oscillator signal generated in a first phase locked loop. A second local oscillator signal is generated in a second phase locked loop. Third and fourth phase locked loops provide inputs to the second phase locked loop to control the second local oscillator frequency. The system and method provides for small step size tuning while maintaining wide phase lock loop bandwidth.

Claims

1. A tuner for receiving RF signals, said tuner comprising:

an input filter receiving an RF signal having a plurality of channels and removing frequencies in said RF signal above an input cutoff frequency;

a first mixer having a first input coupled to said input filter and a second input coupled to a first reference signal, wherein said first mixer generates a first IF signal;

a first IF filter coupled to said first mixer and filtering said first IF signal;

a second mixer having a first input coupled to said first IF filter and a second input coupled to a second reference signal, wherein said second mixer generates a second IF signal;

a coherent reference phase lock loop fed by said second IF signal for generating a third reference signal; and

a frequency synthesizer comprising wide band phase locked loops (PLLs) for generating said first and second reference signals, said frequency synthesizer having a phase noise characteristic that allows said coherent reference phase lock loop to have a narrow loop bandwidth.

2. The tuner of claim 1 wherein said first reference signal provides coarse tuning and wherein said second reference signal provides fine tuning.

3. The tuner of claim 1 wherein said first reference signal provides coarse tuning with step size of greater than 4.5 MHz.

4. The tuner of claim 2 wherein said coarse turning is provided by a single voltage controlled oscillator (VCO) and one of said wide band PLLs providing a highly coherent reference signal suitable for up-converting said signal.

5. The tuner of claim 4 wherein the PLL reference signal is greater than 4.5 MHz.

6. The tuner of claim 1 wherein said second reference signal provides fine tuning with step size less than or equal to 100 Khz.

7. The tuner of claim 6 wherein said fine tuning is provided by three VCOs and three of said wideband PLLs providing a highly coherent reference signal suitable for down-converting said signal.

8. The tuner of claim 7 wherein said three PLLs utilize two reference signals, one greater than 2.25 MHz and the other greater than 4.6 MHZ.

9. The tuner of claim 1 constructed substantially on a single monolithic substrate.

22. The tuner of claim 4 wherein said one wide band PLLs has a bandwidth of approximately 500 Khz.

23. The tuner of claim 7 wherein a first one of said three wideband PLLs has a bandwidth of approximately 200-300 Khz, and the other two of said three wideband PLLs have bandwidths of approximately 300-500 Khz.

28. The tuner of claim 9, wherein said filters are constructed on said single monolithic substrate.

29. The tuner of claim 9, wherein said filters are not constructed on said single monolithic substrate.

10. The method of receiving RF signals comprising the steps of:

removing from an RF signal all frequencies above a cutoff frequency to create a filtered input signal;

creating a first reference frequency signal for mixing with said filtered input signal to establish a first IF signal;

creating a second reference frequency signal for mixing with said first IF signal to create a second IF signal; and

generating said first and second reference signals using a plurality of wideband PLL circuits where said first reference frequency signal achieves coarse tuning and said second reference frequency signal achieves fine tuning.

11. The method of claim 10 wherein said coarse tuning is provided by a single VCO and a wideband PLL providing a highly coherent reference signal.

12. The method of claim 11 wherein the PLL reference signal is greater than 4.5 MHz.

13. The method of claim 10 wherein said fine tuning has a step size less than or equal to 100 Khz.

14. The method of claim 13 wherein said fine tuning is provided by three VCOs and wideband PLLs providing a highly coherent reference signal.

15. The method of claim 14 wherein said PLLs utilize two reference signals, one greater than 2.25 MHz and the other greater than 4.5 MHz.

16. The method of claim 11 wherein said coarse and fine tuning are controlled substantially on a single monolithic circuit.

24. The method of claim 11 wherein said wideband PLL has a bandwidth of approximately 500 Khz.

25. The method of claim 14 wherein a first one of said three wideband PLLs has a bandwidth of approximately 200-300 Khz, and the other two of said three wideband PLLs have bandwidths of approximately 300-500 Khz.

30. The method of claim 10 wherein said coarse and fine tuning are controlled substantially on a single monolithic circuit.

31. The method of claim 14 wherein said coarse and fine tuning are controlled substantially on a single monolithic circuit.

17. A circuit for use in a system for selecting frequencies within a broad band, each said selected frequency having its own bandwidth, such providing first and second reference signals, said circuit comprising:

a plurality of wideband PLLs, wherein a first wideband PLL accepts a reference signal which is out of said band width of each selected frequency, said wideband PLLs having low phase noise and a step size resolution smaller than the loop band width of the individual wideband PLLs; and

wherein said wideband PLLs operate from input reference signals, some of which are out of said bandwidth, and at least one of which is within said band width and wherein said one within said bandwidth is isolated from said output reference signals.

18. The circuit of claim 17 wherein a first one of said wideband PLLs provides coarse frequency resolution under control of said out of band input reference signal and wherein the step size of said coarse resolution is equal to said out of band input reference signal.

19. The circuit of claim 18 wherein a second set of wideband PLLs provides fine frequency resolution under control of a combination of said out of band input reference signals and said at least one isolated in band input reference signal.

20. The circuit of claim 17 constructed as a monolithic circuit.

21. The circuit of claim 17 wherein a plurality of said circuits are constructed substantially on the same monolithic circuit.

26. The circuit of claim 18 wherein said first one of said wideband PLLs has a loop band width of approximately 500 Khz.

27. The circuit of claim 19 wherein said second set of wideband PLLs comprises three wideband PLLs, wherein a first one of said three wideband PLLs has a bandwidth of approximately 200-300 Khz, and the other two of said three wideband PLLs have bandwidths of approximately 300-500 Khz.