Power consumption reduction in medical devices by employing pipeline architecture

• US 6,163,721 A
• Filed: 04/09/1999
• Issued: 12/19/2000
• Est. Priority Date: 04/29/1998
• Status: Expired due to Term

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Thompson, David L.
• Primary Examiner(s): Getzow, Scott M.
• Application Number:
  US09/289,502
• Time in Patent Office: 620 Days
• Field of Search: 607/2, 607/9, 607/5, 395/750.03, 395/750.04, 395/750.07, 395/800.32, 395/800.33, 395/800.34, 395/556, 395/555, 395/557
• US Class Current: 607/2
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/37276 characterised by means for reducing power consumption during telemetry
• CPC Class Codes: A61N 1/378 Electrical supply

Abstract

Power consumption in medical and battery powered devices is reduced through the use and operation of pipeline architecture in a digital signal processor, microcontroller or microprocessor by operating such devices at clock frequencies tailored to conserve power while preserving computational and executional performance. The digital signal processor, microcontroller or microprocessor can be operated at lower clock frequencies relative to those that would be required by one of such processors to complete the multiple functions within a predetermined time period but having no pipeline architecture. With reduced clock frequency, power consumption is reduced. Further, with reduced clock speed, supply voltages applied to such processors may also be reduced.

Claims

1. A medical device comprising:

at least one circuit operable to execute a plurality of instructions, the at least one circuit comprising a processing device, the processing device being operable to execute the plurality of instructions, each of the plurality of instructions being executed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of instructions is executed, the processing device being operable to operate simultaneously upon each of two or more instructions such that substantially the entire associated predetermined time period is used to execute at least one instruction prior to the subsequent time period in which another of the plurality of instructions is executed, the at least one circuit being operable for executing at least one of the plurality of instructions during a predetermined number of clock cycles, each of the plurality of instructions comprising at least first and second portions, the at least one circuit comprising pipeline circuitry capable of substantially simultaneously receiving and outputting in parallel at least one of each of the corresponding respective portions of two or more of the plurality of instructions;

a clock source for providing clock signals at a plurality of clock frequencies, the clock source being operatively connected to control the at least one circuit at a clock frequency such that substantially the entire predetermined time period is used to execute the at least one instruction, the at least one instruction being executed just prior to the subsequent time period;

wherein the clock frequency is such that the power consumed within the predetermined time period by the at least one circuit in performance of executing each of the plurality of instructions is less than the power that would be consumed if the at least one circuit comprised no pipeline circuitry and were to receive, execute and output each of the plurality of instructions serially.

2. The device of claim 1, wherein the predetermined time period is based on physiological events.

3. The device of claim 2, wherein the at least one time period is a time period selected from the group consisting of a blanking interval, an upper rate interval, an escape interval, a refractory interval, a pulse generator/programmer handshake, and a cardiac event.

4. The device of claim 1, wherein the device further includes one or more supply voltage sources to provide one or more supply voltages, the one or more supply voltage sources being operatively connected to the at least one circuit such that a supply voltage is applied thereto as a function of the clock frequency applied thereto.

5. The device of claim 4 wherein the at least one circuit comprises at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, each of the first and second logic circuits being operated at a different clock frequency, each of the logic circuits having a different supply voltage applied thereto based on the different clock frequencies used to control the first and second logic circuits.

6. The device of claim 5, wherein the at least one circuit is operable to perform a plurality of functions, each of at least two of the plurality of functions being performed at different clock frequencies, a voltage generation circuit providing a supply voltage for application to the processing device, the supply voltage being adjusted such that a first supply voltage is provided to the processing device during performance of one of the at least two functions and a second supply voltage is provided to the processing device during performance of the other function, the first and second supply voltages being applied according to different clock frequencies used to control the processing device.

7. The device of claim 6, wherein the voltage generation circuit is a charge pump circuit for generating the second fixed supply voltage based on the first fixed supply voltage.

8. The device of claim 6, wherein the first supply voltage ranges between about 0.8 volts and about 1.5 volts.

9. The device of claim 6, wherein the second supply voltage ranges between about +/-2.0 volts and about +/-3.0 volts.

10. The device of claim 1, wherein the at least one circuit receives at least one analog input.

11. The device of claim 10, wherein the at least one analog input is a cardiac sense signal.

12. The device of claim 6, wherein at least one of the first and second functions is selected from the group of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

13. The device of claim 1, wherein the device is an hermetically sealed implantable medical device.

14. The device of claim 13, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

15. The device of claim 1, wherein at least one of the first and second digital processing systems comprise circuits of a type selected from the group consisting of CMOS circuits, CML circuits, SOS circuits, SOI circuits, BICMOS circuits, PMOS circuits and NMOS circuits.

16. The device of claim 1, further comprising one or more digital circuits.

17. The device of claim 16, wherein the device further includes means for adjusting the back gate bias of at least one of the one or more digital circuits.

18. The device of claim 16, wherein the one or more digital circuits include one or more of a processor, a controller and a memory.

19. The device of claim 1, further comprising one or more analog circuits.

20. The device of claim 19, wherein at least one of the one or more analog circuits includes at least one of an atrial sense amplifier, a ventricular sense amplifier, a T-wave amplifier, one or more bandpass filters, one or more detection circuits, one or more sensor amplification circuits, one or more physiological signal amplification circuits, one or more output circuits, a battery monitor circuit, and a power on reset circuit.

21. The device of claim 19, wherein at least one of the one or more analog circuits includes at least one amplifier circuit for amplifying the one or more analog signals.

22. The device of claim 19, further comprising one or more digital circuits.

23. The device of claim 22, wherein the device further includes a level shifter to translate signals between the one or more analog circuits and the one or more digital circuits.

24. The device of claim 1, wherein the processing device comprises at least one digital signal processor.

25. The device of claim 1, wherein the processing device comprises first and second digital signal processors, a supply voltage source being operatively connected to provide a first supply voltage to the first digital signal processor and a second supply voltage to the second digital signal processor, the first and second supply voltages being such that the power consumed by the first and second digital signal processors in executing corresponding first and second sets of instructions in the predetermined time period is less than the power that would be consumed if only one of the first and second digital signal processors were to execute both the first and second sets of instructions within the predetermined time period.

26. The device of claim 25, wherein the device further includes a clock circuit for providing a first and second clock frequency to control operation of the first and second digital signal processors during execution of the first set of instructions and the second set of instructions, respectively, and further wherein the first and second clock frequencies are such that the power consumed by the first and second digital signal processors in executing the first and second sets of instructions during the predetermined time period is less than the power that would be consumed if only one of the first and second digital signal processors were to execute both of the first and second sets of instructions within the predetermined time period.

27. The device of claim 26, wherein the levels of the first and second supply voltages are applied on the basis of the first and second clock frequencies, respectively.

28. The device of claim 25, wherein the first set of instructions is executed at a clock frequency about equal to the clock frequency used for executing the second set of instructions, and further wherein the first and second supply voltages are about equal.

29. The device of claim 25, wherein at least one of the instructions in the first and second sets of instructions corresponds to a function selected from the group consisting of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

30. The device of claim 1, wherein the processing device comprises at least processing device selected from the group consisting of a microprocessor, a digital signal processor and a microcontroller.

31. The device of claim 30, wherein a supply voltage source is operatively connected to provide a supply voltage to the at least one processing device, the supply voltage being such that the power consumed by the at least one processing device in executing the at least one instruction in the predetermined time period is less than the power that would be consumed if one or more processing devices similar to the at least one processing device but having no pipeline circuitry therein were to receive, execute and output each of the plurality of instructions serially and further execute the instruction within the predetermined time period.

32. The device of claim 1, wherein at least one of the plurality of instructions corresponds to a function selected from the group of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

33. The device of claim 1, wherein the at least one circuit comprises one or more circuits of a type selected from the group consisting of a CMOS circuit, a CML circuit, an SOS circuit, an SOI circuit, a BICMOS circuit, a PMOS circuit and an NMOS circuit.

34. A method of conserving power in a medical device, the method comprising:

providing at least one circuit operable to execute a plurality of instructions, the at least one circuit comprising a processing device, the processing device being operable to execute the plurality of instructions, each of the plurality of instructions being executed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of instructions is executed, the processing device being operable to operate simultaneously upon each of two or more instructions such that substantially the entire associated predetermined time period is used to execute at least one instruction prior to the subsequent time period in which another of the plurality of instructions is executed, the at least one circuit being operable for executing at least one of the plurality of instructions during a predetermined number of clock cycles, each of the plurality of instructions comprising at least first and second portions, the at least one circuit comprising pipeline circuitry capable of substantially simultaneously receiving and outputting in parallel at least one of each of the corresponding respective portions of two or more of the plurality of instructions;

providing a clock source for providing clock signals at a plurality of clock frequencies, the clock source being operatively connected to control the at least one circuit at a clock frequency such that substantially the entire predetermined time period is used to execute the at least one instruction, the at least one instruction being executed just prior to the subsequent time period;

operating the clock source at a clock frequency is such that the power consumed within the predetermined time period by the at least one circuit in performance of executing each of the plurality of instructions is less than the power that would be consumed if the at least one circuit comprised no pipeline circuitry and were to receive, execute and output each of the plurality of instructions serially.

35. The method of claim 34, wherein the predetermined time period is based on physiological events.

36. The method of claim 35, wherein the at least one time period is a time period selected from the group consisting of a blanking interval, an upper rate interval, an escape interval, a refractory interval, a pulse generator/programmer handshake, and a cardiac event.

37. The method of claim 34, further comprising providing one or more supply voltage sources to provide one or more supply voltages.

38. The method of claim 37, further comprising operatively connecting the one or more supply voltage sources to the at least one circuit such that a supply voltage is applied thereto as a function of the clock frequency applied thereto.

39. The method of claim 34, wherein the at least one circuit comprises at least a first logic circuit for performing a first function and a second logic circuit for performing a second function, and further wherein the operating step includes:

operating the first logic circuit to perform the first function during a first predetermined time period at a first clock frequency such that substantially the entire first predetermined time period is used by the first logic circuit to perform the first function; and

operating the second logic circuit at a second clock frequency that is different than the first clock frequency such that substantially the entire respective second predetermined time period is used by the second logic circuit to perform the second functions.

40. The method of claim 39, wherein at least one of the first predetermined time period and the second predetermined time period is a time period based on physiological events.

41. The method of claim 40, wherein the at least one of the first and second predetermined time periods are time periods selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

42. The method of claim 34, wherein the at least one circuit comprises a processing device, the processing device operable to perform a plurality of functions, each of the plurality of functions being performed during an associated predetermined time period prior to a subsequent time period in which another of the plurality of functions is performed, and further wherein the operating step includes:

operating the processing device at a clock frequency to perform at least one function of the plurality of functions such that substantially the entire associated predetermined time period for the at least one function is used to complete the first function prior to a subsequent time period in which another of the plurality of functions is performed.

43. The method of claim 42, wherein the associated predetermined time period is a time period based on physiological events.

44. The method of claim 43, wherein the associated time period is a time period selected from a group of time periods associated with cardiac events including blanking interval, upper rate interval, escape interval, refractory interval, and pulse generator/programmer handshake.

45. The method of claim 34, wherein the method further includes controlling the level of a supply voltage applied to the at least one circuit as a function of the clock frequency.

46. The method of claim 38, wherein a charge pump circuit for generating the second supply voltage based on the first supply voltage is provided.

47. The method of claim 46, wherein the first supply voltage ranges between about 0.8 volts and about 1.5 volts.

48. The method of claim 46, wherein the second supply voltage ranges between about +/-2.0 volts and about +/-3.0 volts.

49. The method of claim 34, wherein the at least one circuit receives at least one analog input.

50. The method of claim 49, wherein the at least one analog input is a cardiac sense signal.

51. The method of claim 39, wherein at least one of the first and second functions is selected from the group of capture detection, R-wave detection, P-wave detection, T-wave detection, electromagnetic interference detection, oxygen saturation determination, pressure determination, sensor cardiac contractility determination, cardiac flow determination, telemetry reception and telemetry transmission.

52. The method of claim 34, wherein the device is an hermetically sealed implantable medical device.

53. The method of claim 52, wherein the implantable medical device is selected from the group consisting of an implantable stimulator, an implantable nerve stimulator, an implantable pacemaker, an IPG, an implantable cardioverter, an implantable PCD, an implantable defibrillator, an implantable ICD and an implantable drug pump.

54. The method of claim 34, wherein the at least one circuit comprises a circuit of a type selected from the group consisting of a CMOS circuit, a CML circuit, an SOS circuit, an SOI circuit, a BICMOS circuit, a PMOS circuit and an NMOS circuit.

55. The method of claim 34, further comprising providing one or more digital circuits for the at least one circuit.

56. The method of claim 55, wherein the device further includes providing means for adjusting the back gate bias of at least one of the one or more digital circuits.

57. The method of claim 55, wherein the one or more digital circuits include one or more of a processor, a controller and a memory.

58. The method of claim 34, further comprising providing one or more analog circuits.

59. The method of claim 58, wherein at least one of the one or more analog circuits includes at least one of an atrial sense amplifier, a ventricular sense amplifier, a T-wave amplifier, one or more bandpass filters, one or more detection circuits, one or more sensor amplification circuits, one or more physiological signal amplification circuits, one or more output circuits, a battery monitor circuit, and a power on reset circuit.

60. The method of claim 58, wherein at least one of the one or more analog circuits includes at least one amplifier circuit for amplifying the one or more analog signals.

61. The method of claim 34, wherein the method further includes controlling the level of a supply voltage applied to the at least one circuit as a function of the clock frequency.

62. The method of claim 34, further comprising the step of providing at least one of at least one digital signal processor, at least one microprocessor and at least one microcontroller for incorporation into the at least one circuit.

63. The method of claim 58, wherein the step of providing the one or more analog circuits includes the step of providing at least one of an atrial sense amplifier, a ventricular sense amplifier, a T-wave amplifier, one or more bandpass filters, one or more detection circuits, one or more sensor amplification circuits, one or more physiological signal amplification circuits, one or more output circuits, a battery monitor circuit, and a power on reset circuit.