Method for calibrating variable delay circuit and a variable delay circuit using the same
First Claim
1. A method for calibrating, for a nominal amount of delay Dsk =ds k, k=0, 1, 2, . . . , K, for each nominal minimum delay step ds, a variable delay circuit in which the state of a cascade connection of M differently weighted delay stages is selectively controlled by a desired one of control signal values CCi from O to K to thereby set a desired amount of delay of said variable delay circuit, said M and K being integers equal to or greater than 2, said method comprising the steps of:
- (a) predefining in a memory an at least K-row calibration table having columns for holding errors and control signal values which provide the errors;
(b) measuring the amount of delay Di of said variable delay circuit set by said control signal value CCi ;
(c) dividing said measured amount of delay Di by said minimum nominal step ds and calculating an integral part k of the resulting quotient and first and second errors Rk =Di -dsk and Rk+1 =ds -Rk of said measured amount of delay Di with respect to two adjoining nominal amounts of delay Dsk and Dsk+1 ;
(d) making a check to determine if said calculated first error Rk is smaller than an error held in a k-th row of said calibration table, and if so, writing said calculated first error Rk and the corresponding control signal value CCi over previous data in the column of said k-th row;
(e) making a check to determine if said calculated second error Rk+1 is smaller than an error held in a (k+1)-th column of said calibration table, and if so, writing said calculated second error Rk+1 and the corresponding control signal values CCi over previous data in the column of said (k+1)-th row; and
(f) executing said steps (b) to (e) from i=0 to i=2M -1, thereby obtaining, in O-th to K-th rows of said calibration table, control signal values which minimize error with respect to said nominal amount of delay.
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Accused Products
Abstract
In a variable delay circuit calibrating method in which the state of connection of M delay stages connected in cascade through multiplexers and weighted differently is controlled by a control signal value to generate a calibrated amount of delay corresponding to a nominal amount of delay Ds which varies in a predetermined minimum nominal delay step ds, the method comprises the steps of: dividing an amount of delay Di measured for each given control signal value CCi by the minimum nominal delay step ds of a variable delay circuit; calculating first and second errors, Rk =Di -ds k and Rk+1 =ds -Rk, between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay Dsk and Dsk+1 ; making a check to determine if the first error Rk is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error Rk and the corresponding control signal value CCi over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error Rk+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; and, if so, writing the second error Rk+1 and the corresponding control signal value CCi over the existing values in the column of the (k+1)-th row of the calibration table. By repeatedly executing these steps for i=0 to i=2M -1, control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.
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Citations
8 Claims
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1. A method for calibrating, for a nominal amount of delay Dsk =ds k, k=0, 1, 2, . . . , K, for each nominal minimum delay step ds, a variable delay circuit in which the state of a cascade connection of M differently weighted delay stages is selectively controlled by a desired one of control signal values CCi from O to K to thereby set a desired amount of delay of said variable delay circuit, said M and K being integers equal to or greater than 2, said method comprising the steps of:
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(a) predefining in a memory an at least K-row calibration table having columns for holding errors and control signal values which provide the errors; (b) measuring the amount of delay Di of said variable delay circuit set by said control signal value CCi ; (c) dividing said measured amount of delay Di by said minimum nominal step ds and calculating an integral part k of the resulting quotient and first and second errors Rk =Di -dsk and Rk+1 =ds -Rk of said measured amount of delay Di with respect to two adjoining nominal amounts of delay Dsk and Dsk+1 ; (d) making a check to determine if said calculated first error Rk is smaller than an error held in a k-th row of said calibration table, and if so, writing said calculated first error Rk and the corresponding control signal value CCi over previous data in the column of said k-th row; (e) making a check to determine if said calculated second error Rk+1 is smaller than an error held in a (k+1)-th column of said calibration table, and if so, writing said calculated second error Rk+1 and the corresponding control signal values CCi over previous data in the column of said (k+1)-th row; and (f) executing said steps (b) to (e) from i=0 to i=2M -1, thereby obtaining, in O-th to K-th rows of said calibration table, control signal values which minimize error with respect to said nominal amount of delay. - View Dependent Claims (2, 3, 4)
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5. A variable delay circuit which generates a delay calibrated by a control signal value in correspondence with a nominal amount of delay Dsk for each nominal minimum delay step ds, said variable delay circuit comprising:
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M delay stages of differently weighted amounts of delay; M multiplexers connected to the outputs of said M delay stages, respectively, for selectively outputting inputs to and outputs from said delay stages, said M delay stages and said M multiplexers being connected in cascade; control signal converting means responsive to a control signal fed thereto, for generating desired control signal values from O to K and applying them to said multiplexers to set in said M delay stages desired amounts of delay corresponding to nominal amounts of delay Dsk =ds k (k=0, 1, 2, . . . , K) for each nominal minimum delay step, said M and K being integers equal to or greater than 2; delay time measuring means for measuring the delay time between the input and output of said variable delay circuit upon each change of said control signal values from O to K; a memory having defined therein an at least K-row calibration table with columns for prestoring an error and a control signal value which provides said error; and calculating means for;
dividing an amount of delay Di measured for each given control signal value CCi by the minimum nominal delay step ds of a variable delay circuit;
calculating first and second errors, Rk =Di -ds k and Rk+1 =ds -Rk, between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay Dsk and Dsk+1 ;
making a check to determine if the first error Rk is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k;
if so, writing the first error Rk and the corresponding control signal value CCi over the existing values in the column of the k-th row of the calibration table;
making a check to determine if the second error Rk+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1;
if so, writing the second error Rk+1 and the corresponding control signal value CCi over the existing values in the column of the (k+1)-th row of the calibration table; and
repeatedly executing these operations for i=0 to i=2M -1, whereby control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS. - View Dependent Claims (6, 7, 8)
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Specification