On-chip test circuit for evaluating an on-chip signal using an external test signal

• US 6,163,862 A
• Filed: 12/01/1997
• Issued: 12/19/2000
• Est. Priority Date: 12/01/1997
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Adams, R. Dean, Cooley, Edmond S., Hansen, Patrick R.
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US08/980,524
• Time in Patent Office: 1,114 Days
• Field of Search: 714/718, 714/719, 714/721, 714/733, 714/734, 714/735, 714/736, 365/201
• US Class Current: 714/718
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

An on-chip test circuit for evaluating on-chip signals for a semiconductor memory chip includes an on-chip signal associated with a memory circuit on the chip; said on-chip signal having a signal characteristic to be evaluated; an input circuit for receiving an off-chip test signal; and a test circuit that compares said on-chip signal and said test signal.

Claims

1. A semiconductor chip comprising:

an on-chip signal;

said on-chip signal having an analog voltage to be evaluated; and

a test circuit that receives an off-chip test signal having an analog voltage and detects the relative magnitude of said analog voltage of said on-chip signal and said analog voltage of said test signal to evaluate the voltage level of the on-chip signal.

2. The chip of claim 1 comprising a memory circuit.

3. The chip of claim 2 wherein said test circuit comprises a sense amplifier.

4. The chip of claim 1 comprising input control logic to reduce power consumption when said test circuit is idle.

5. The chip of claim 1 wherein said on-chip signal comprises a single ended signal.

6. The chip of claim 1 wherein said on-chip signal comprises a differential signal.

7. The chip of claim 6 wherein said differential signal is input to a differential sense amplifier.

8. The chip of claim 7 wherein said differential sense amplifier comprises a first pair of sense transistors;

and said differential signal is applied to said first pair of sense transistors.

9. The chip of claim 8 comprising a second pair of sense transistors, each of said second pair sense transistors being in parallel with a respective one of said first pair of sense transistors;

said test signal comprising a differential test signal and being applied to said second pair of sense transistors;

said sense amplifier producing an output that indicates said on-chip signal exceeds said test signal.

10. The chip of claim 8 wherein said differential sense amplifier is connected to a pair of bit lines of a memory array.

11. The chip of claim 10 wherein said sense amplifier operates to READ data for memory cell connectable to said bit lines.

12. The chip of claim 1 wherein said test signal is applied iteratively to vary with each iterative step a characteristic of said test signal;

said test circuit producing in response to said test signal an output that indicates said signal characteristic based on each iterative step.

13. The chip of claim 12 wherein said test circuit comprises a sense amplifier connected to a pair of bit lines of a memory array on the chip;

said on-chip signal comprising a differential input signal on said bit lines;

said test signal being applied as a test voltage that varies with time in a predetermined manner such that said sense amplifier output state indicates said on-chip signal being greater than said test signal.

14. The chip of claim 1 wherein said test circuit operates to evaluate said signal characteristic at different points in time to thereby evaluate an on-chip signal waveform.

15. A method for evaluating an on-chip signal having an analog voltage for a semiconductor chip, comprising the steps of:

a) applying an externally generated test signal having an analog voltage to one input of a test circuit on the chip;

b) applying the on-chip signal being evaluated to another input of the test circuit;

c) detecting by said test circuit the relative magnitude of said on-chip signal analog voltage and the analog voltage of said test signal; and

d) producing an output from the test circuit that indicates the greater magnitude of the analog voltage of the on-chip signal and the analog voltage of the test signal.

16. The method of claim 15 wherein the test signal is applied in an iterative manner with a characteristic of the test signal being changed with each iteration.

17. The method of claim 16 wherein on-chip analog signal voltage level is determined by detecting said on-chip voltage exceeding said test voltage during one of said iterations.

18. The method of claim 17 wherein said on-chip signal comprises a differential signal on a pair of bit lines connected to a memory array.

19. The method of claim 18 wherein a sense amplifier is used to compare said differential signal with a differential test signal with the sense amplifier output state being determined by the relative magnitude of said differential signal and said differential test signal.

20. The method of claim 15 wherein said step of comparing said on-chip signal with said test signal is performed iteratively at different points in time to evaluate an on-chip signal waveform.