Method of planarizing thin film layers deposited over a common circuit base

• US 6,165,892 A
• Filed: 07/31/1998
• Issued: 12/26/2000
• Est. Priority Date: 07/31/1998
• Status: Expired due to Fees

• Current Assignee: Kulicke and Soffa Industries Incorporated
• Original Assignee: Kulicke & Soffa Holdings, Inc.
• Inventors: Kaplan, Todd S., Skinner, Michael P., Chazan, David J., Strandberg, Jan I., Chen, Ted T., Lykins, James L.
• Primary Examiner(s): Picardat, Kevin M.
• Assistant Examiner(s): COLLINS, DEVEN M
• Application Number:
  US09/127,580
• Time in Patent Office: 879 Days
• Field of Search: 438/623, 438/622, 438/618, 438/584
• US Class Current: 438/623
• CPC Class Codes: H01L 21/481 Insulating layers on insulating parts, with or without metallisation
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 23/5383 Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2201/0195 Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09881 Coating only between conductors, i.e. flush with the conductors
• CPC Class Codes: H05K 2203/0585 Second resist used as mask for selective stripping of first resist
• CPC Class Codes: H05K 2203/0759 Forming a polymer layer by liquid coating, e.g. a non-metallic protective coating or an organic bonding layer
• CPC Class Codes: H05K 2203/1476 Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
• CPC Class Codes: H05K 3/0023 by exposure and development of a photosensitive insulating layer
• CPC Class Codes: H05K 3/0032 of organic insulating material
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4673 : Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer similar methods for protective coatings H05K3/28

Abstract

A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

Claims

1. A method for forming a high density interconnect scheme on a common circuit base to connect a first integrated circuit to a second integrated circuit and/or to support components, said method comprising:

(a) providing a common circuit base having first and second patterned conductive layers formed thereon and having an upper surface, said common circuit base also having at least one trench formed on said upper surface between raised features of said first conductive layer;

(b) forming a first layer of a dielectric film over said common circuit base and over said raised features and said trenches;

(c) patterning said first layer to remove portions of said first layer formed over said raised features;

(d) forming a second layer of said dielectric film over said patterned first dielectric layer;

(e) performing additional film deposition and film patterning steps to complete the layout of a thin film interconnect structure over said common circuit base; and

(f) attaching an integrated circuit die to said common circuit base and electrically connecting said integrated circuit die to said thin film interconnect structure.

2. The method of claim 1 wherein said first and second dielectric layers are formed by a spin coating film deposition step.

3. The method of claim 1 further including the step of attaching a second integrated circuit die to said common circuit base and electrically connecting said second integrated circuit die to said thin film interconnect structure.

4. A method for forming a planarized dielectric film on a surface of a common circuit base having raised features formed on said surface and defining a trench between said raised features, said method comprising:

(a) forming a first layer of said dielectric film over said common circuit base and over said raised features and said trench;

(b) patterning said first layer to remove portions of said layer formed over said raised features;

(c) forming a second layer of said dielectric film over said patterned first dielectric layer.

5. The method of claim 4 wherein said first layer is patterned to expose portions of said raised features.

6. The method of claim 4 wherein said first layer of said dielectric film is a photo-definable material and wherein said first layer is patterned by an expose and develop sequence in which said dielectric material is exposed to light through a patterned mask and then developed with a developing solution selected for said photo-definable material.

7. The method of claim 6 wherein said expose and develop sequence is a negative develop process and wherein said mask mirrors said raised features.

8. The method of claim 6 wherein said photo-definable material comprises a cardo acrylate material.

9. The method of claim 8 wherein said cardo acrylate material comprises Nippon Steel Chemical V-259PA.

10. The method of claim 6 wherein said expose and develop sequence uses a negative bias mask during the expose phase of the sequence.

11. The method of claim 10 wherein said negative biased mask is biased between about 3 to 5 microns from edges of the raised features.

12. The method of claim 4 wherein said first layer of said dielectric film is a nonphoto-definable material and wherein said first layer is patterned by forming a layer of photoresist over said first layer and using an expose and develop sequence in which said photoresist layer is exposed to ultraviolet light through a patterned mask and then developed with a developing solution selected for said photoresist.

13. The method of claim 4 wherein said first layer of said dielectric film is a nonphoto-definable material and wherein said first layer is patterned by laser ablation techniques.

14. A method according to claim 4 where the common circuit base comprises a printed wiring board (PWB).

15. The method according to claim 14 wherein said printed wiring board (PWB) comprises:

(i) first and second organic polymer laminate insulating layers;

(ii) a first conductive layers formed on an upper surface of the first laminate insulating layer and a second conductive layer formed on a lower surface of the second laminate insulating layer; and

(iii) plated through holes electrically connecting said first conductive layer with said second conductive layer.

16. The method of claim 15 wherein said PWB is a four-layer PWB.

17. The method according to claim 4 wherein said common circuit base has a total surface area of about 1400 cm² or more.

18. A method for forming a planarized dielectric film on a surface of a common circuit base having raised features formed on said surface and defining a trench between said raised features, said method comprising:

(a) forming a first layer of said dielectric film over said common circuit base and over said raised features and said trench, wherein said first layer of said dielectric film is a photo-definable material that comprises a polymer dielectric and a solvent;

(b) thereafter, baking said first layer to remove at least some of said solvent material from said first dielectric layer;

(c) thereafter, exposing said first dielectric layer to patterned light;

(d) thereafter, developing said exposed first dielectric layer to etch away portions of said first dielectric layer formed over said raised features;

(e) thereafter, curing said developed first dielectric layer; and

(f) thereafter, forming a second layer of said dielectric film over said developed first dielectric layer.

19. The method of claim 18 wherein said first layer is baked at a temperature of between 75 and 100°

C. in a convection oven for between 3 and 30 minutes to remove solvent from said layer.

20. The method of claim 18 wherein said first layer is baked at a temperature of between 130 and 200°

C. in a convection oven for between 45 and 90 minutes to cure said layer.

21. The method according to claim 18 wherein the common circuit base comprises a printed wiring board (PWB) and wherein said printed wiring board (PWB) comprises:

(i) first and second organic polymer laminate insulating layers;

(ii) a first conductive layers formed on an upper surface of the first laminate insulating layer and a second conductive layer formed on a lower surface of the second laminate insulating layer; and

(iii) plated through holes electrically connecting said first conductive layer with said second conductive layer.