Programmable analog arithmetic circuit for imaging sensor

• US 6,166,367 A
• Filed: 03/26/1999
• Issued: 12/26/2000
• Est. Priority Date: 03/26/1998
• Status: Expired due to Term

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Photobit Corporation (Micron Technology, Inc.)
• Inventors: Cho, Kwang-Bo (Austin)
• Primary Examiner(s): Epps, Georgia
• Assistant Examiner(s): Spector, David N.
• Application Number:
  US09/277,617
• Time in Patent Office: 641 Days
• Field of Search: 250/208.1, 348/241, 348/250, 348/294, 348/302-304, 348/307-311, 348/315, 341/155
• US Class Current: 250/208.1
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

A programmable arithmetic circuit to form multiple circuit modules for different arithmetic operations that share certain common electronic elements to reduce the number of elements. Such circuit can be integrated to an imaging sensor array such as a CMOS active pixel sensor array to form arithmetic operations and analog-to-digital conversion for imaging processing.

Claims

1. A semiconductor imaging device, comprising:

a substrate formed of a semiconductor material;

a sensor array of photosensitive elements on said substrate to convert an image into pixel signals;

a reconfigurable arithmetic circuit, formed on said substrate, having a plurality of circuit elements and a plurality of switches to perform first and second arithmetic operations on said pixel signals; and

a control circuit coupled to control a first set of said switches in said reconfigurable arithmetic circuit to couple a first set of said circuit elements to form a first circuit to perform said first arithmetic operation, and to control a second set of said switches to couple a second set of circuit elements which includes at least part of said first set of circuit elements to form a second circuit to perform said second arithmetic operation.

2. A device as in claim 1, wherein one of said first and second circuits is operable to select a block of pixels in said sensor array and to produce a block average of pixel electrical signals of said block.

3. A device as in claim 1, wherein one of said first and second circuits is operable to select a block of pixels in said sensor array and to produce a block sum of pixel electrical signals of said block.

4. A device as in claim 1, wherein one of said first and second circuits effects an analog-to-digital converter to convert said pixel electrical signals into digital form.

5. A device as in claim 1, wherein said photosensitive elements include active pixel sensors, with CMOS image sensor parts, and an in-pixel buffer circuit and an in-pixel select transistor.

6. A device as in claim 1, wherein said sensor array is a CMOS active pixel sensor array.

7. A method for operating a circuit to process signals from an imaging sensor array on an image sensor substrate, comprising:

coupling a first set of circuit elements, on the image sensor array substrate, to form a first circuit to perform a first signal operation that changes a signal from the imaging sensor array; and

coupling a second set of circuit elements, on the image sensor substrate, different from said first set bu including at least one common element from said first set, to form a second circuit to perform a second signal operation.

8. A method as in claim 7, wherein said common circuit element includes an amplifier.

9. A method as in claim 7, wherein said first circuit is a block summing circuit to produce a sum of selected adjacent pixels and said second circuit is a block averaging circuit to produce an average of selected adjacent pixels.

10. A semiconductor imaging device, comprising:

a substrate;

a sensor array of pixels, on said substrate, to detect an input image, wherein each pixel is configured to produce a pixel signal indicative of a total of photo-induced pixel signal and non-photon-induced background signal and a pixel reset signal indicative of said non-photon-induced background signal;

a reconfigurable arithmetic circuit, on said substrate, having an array of column-parallel arithmetic cells respectively coupled to columns of said sensor array and reconfigurable to form different arithmetic circuits to perform arithmetic operations on signals from said sensor array, each arithmetic cell comprising;

(1) a first signal sampling capacitor to receive said pixel signal and a first reset sampling capacitor to receive said pixel reset signal,

(2) a first switched capacitor integrator having a signal channel coupled to said first signal sampling capacitor and a reset channel coupled to said first reset sampling capacitor,

(3) a second signal sampling capacitor and a second reset sampling capacitor respectively coupled to said signal and reset channels of said first switched capacitor integrator,

(4) a second switched capacitor integrator having a signal channel and a reset channel respectively coupled to said second signal sampling capacitor and second reset sampling capacitor,

(5) a plurality of electronic switches coupled to control said sampling capacitors and said integrators and their interconnections,

(6) a plurality of communication channels having switches to couple each arithmetic cell to at least one adjacent arithmetic cell; and

a control circuit, on said substrate, coupled to said arithmetic cells and to control each arithmetic cell to perform at least addition, subtraction, multiplication, and division operations on signals from said sensor array.

11. A device as in claim 10, wherein each of said electronic swithes includes a transistor which has a gate coupled to receive a control signal caused by said control circuit.

12. A device as in claim 10, wherein said sensor array is an active pixel array, each pixel having a CMOS image sensor, an in-pixel buffer, and an in-pixel select transistor.

13. A device as in claim 10, wherein said communication channels include:

a first signal communication channel to couple one terminal of said first signal sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding first signal sampling capacitor in said at least one adjacent arithmetic cell;

a first reset communication channel to couple one terminal of said first reset sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding first reset sampling capacitor in said at least one adjacent arithmetic cell;

a second signal communication channel to couple one terminal of said second signal sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding second signal sampling capacitor in said at least one adjacent arithmetic cell; and

a second reset communication channel to couple one terminal of said second reset sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding second reset sampling capacitor in said at least one adjacent arithmetic cell.

14. A device as in claim 10, wherein said first switched capacitor integrator includes a signal integrating capacitor in said signal channel and a reset integrating capacitor in said reset channel, and

wherein said communication channels include a signal capacitor channel to couple one terminal of said signal integrating capacitor in said arithmetic cell to a corresponding terminal of a corresponding signal integrating capacitor in said at least one adjacent arithmetic cell and reset capacitor channel to couple one terminal of said reset integrating capacitor in said arithmetic cell to a corresponding terminal of a corresponding reset integrating capacitor in said at least one adjacent arithmetic cell.

15. A device as in claim 10, further comprising:

a signal channel feedback loop having a switch and coupled to feed a signal output from said second switched capacitor integrator to a signal input of said first switched capacitor integrator; and

a reset channel feedback loop having a switch and coupled to feed a reset output from said second switched capacitor integrator to a reset input of said first switched capacitor integrator.

16. A semiconductor imaging device, comprising:

a sensor array of pixels to detect an input image, wherein each pixel is configured to produce a pixel signal indicative of a total of photo-induced pixel signal and non-photo-induced background signal and a pixel reset signal indicative of said non-photo-induced background signal;

a reconfigurable arithmetic circuit having an array of column-parallel arithmetic cells respectively coupled to columns of said sensor array and reconfigurable to form different arithmetic circuits to perform arithmetic operations on signals from said sensor array, each arithmetic cell comprising,

(1) a first signal sampling capacitor to receive said pixel signal and a first reset sampling capacitor to receive said pixel reset signal,

(2) a first switched capacitor integrator having a signal channel coupled to said first signal sampling capacitor and a reset channel coupled to said first reset sampling capacitor,

(3) a second signal sampling capacitor and a second reset capacitor respectively coupled to said signal and reset channels of said first switched capacitor integrator,

(4) a second switched capacitor integrator having a signal channel and a reset channel respectively coupled to said second signal sampling capacitor and second reset capacitor, and

(5) a comparator coupled to said second switched capacitor integrator; and

a control circuit coupled to control a selected block of arithmetic cells to form a block summing circuit based on said first and second switched capacitor integrators and to form a block averaging circuit based on said first switched capacitor integrator in said selected block, and to control each arithmetic cell to form a cyclic analog-to-digital converter based on said first, second switched capacitor integrator, and said comparator.

17. A device as in claim 16, further comprising a semiconductor substrate and wherein said sensor array and said arithmetic circuit are formed on said semiconductor substrate.

18. A device as in claim 17, wherein said arithmetic circuit is a CMOS circuit.

19. A device as in claim 17, wherein said sensor array is an active pixel array.

20. A semiconductor imaging device, comprising:

a substrate;

a sensor array of pixels, on said substrate, to detect an input image, wherein each pixel is configured to produce a pixel signal in response to received photons;

a reconfigurable arithmetic circuit, on said substrate, having an array of column-parallel arithmetic cells respectively coupled to columns of said sensor array and reconfigurable to form different arithmetic circuits to perform arithmetic operations on signals from said sensor array, each arithmetic cell comprising;

(1) a first signal sampling capacitor to receive said pixel signal,

(2) a first switched capacitor integrator coupled to said first signal sampling capacitor,

(3) a second signal sampling capacitor coupled to said first switched capacitor integrator,

(4) a second switched capacitor integrator coupled to said second signal sampling capacitor,

(5) a plurality of electronic switches coupled to control said sampling capacitors and said integrators and their interconnections,

(6) a plurality of communication channels having switches to couple each arithmetic cell to at least one adjacent arithmetic cell; and

a control circuit, on said substrate, coupled to said arithmetic cells and to control each arithmetic cell to perform at least addition, subtraction, multiplication, and division operations on signals from said sensor array.

21. A device as in claim 20, wherein said sensor array is an active pixel array, each pixel having a CMOS image sensor, an in-pixel buffer, and an in-pixel select transistor.

22. A device as in claim 20, wherein said communication channels include:

a first signal communication channel to couple one terminal of said first signal sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding first signal sampling capacitor in said at least one adjacent arithmetic cell; and

a second signal communication channel to couple one terminal of said second signal sampling capacitor in said arithmetic cell to a corresponding terminal of a corresponding second signal sampling capacitor in said at least one adjacent arithmetic cell.

23. A device as in claim 20, wherein said first switched capacitor integrator includes a signal integrating capacitor, and

wherein said communication channels include a signal capacitor channel to couple one terminal of said signal integrating capacitor in said arithmetic cell to a corresponding terminal of a corresponding signal integrating capacitor in said at least one adjacent arithmetic cell.