Integrated circuit having embedded memory with electromagnetic shield

• US 6,166,403 A
• Filed: 11/12/1997
• Issued: 12/26/2000
• Est. Priority Date: 11/12/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Ramesh, Subramanian, Castagnetti, Ruggero, Liu, Yauh-Ching
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Vu, Hung K.
• Application Number:
  US08/967,545
• Time in Patent Office: 1,140 Days
• Field of Search: 257/294, 257/297, 257/340, 257/409, 257/503, 257/508, 257/659, 257/660, 257/662, 257/758, 257/693, 257/208, 257/211, 438/128, 438/129, 438/348, 438/361
• US Class Current: 257/211
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit including a substrate having a memory area and a non-memory area. An embedded memory is fabricated on the substrate within the memory area. First and second semiconductor cells are fabricated on the substrate within the non-memory area. An electromagnetic shield covers substantially memory area. A routing layer is fabricated over the memory and non-memory areas and over the electromagnetic shield. A signal wire is electrically coupled between the first and second semiconductor cells and has a conductive segment which is routed within the routing layer and extends over the memory area.

Claims

1. An integrated circuit comprising:

a substrate having a memory area and a non-memory area;

a voltage supply conductor;

an embedded memory fabricated on the substrate within the memory area;

at least one memory routing layer, which includes a highest memory routing layer relative to the substrate, fabricated within the memory area and electrically coupled to the embedded memory;

first and second semiconductor cells fabricated on the substrate within the non-memory area;

an electromagnetic shield fabricated as an additional, non-routing layer on the integrated circuit over the highest memory routing layer and covering substantially the entire memory area, wherein the electromagnetic shield is electrically coupled to the voltage supply conductor;

a logic routing layer, which is the next-higher routing layer on the integrated circuit above the highest memory routing layer and is fabricated over the memory and non-memory areas and over the electromagnetic shield; and

a signal wire electrically coupled between the first and second semiconductor cells and having a first conductive segment routed within the logic routing layer and extending over the memory area.

2. The integrated circuit of claim 1 wherein the logic routing layer has a thickness and the electromagnetic shield has a thickness which is up to one-half of the thickness of the logic routing layer.

3. The integrated circuit of claim 1 wherein the electromagnetic shield has a thickness of 100 Å

-2500 Å

.

4. The integrated circuit of claim 1 wherein the electromagnetic shield is formed of a conductive sheet of material.

5. The integrated circuit of claim 1 wherein the embedded memory comprises a dynamic random access memory (DRAM).

6. The integrated circuit of claim 1 and further comprising:

a first dielectric layer fabricated between the highest memory routing layer and the electromagnetic shield; and

a second dielectric layer fabricated between the electromagnetic shield and the next-higher logic routing layer.

7. The integrated circuit of claim 1 wherein the voltage supply conductor is fabricated within one of the at least one memory routing layers and the next-higher logic routing layer.

8. The integrated circuit of claim 6 wherein:

the highest memory routing layer comprises a second conductive segment;

the next-higher logic routing layer comprises a third conductive segment;

the electromagnetic shield comprises an aperture; and

the integrated circuit further comprises a conductive via electrically coupled between the second and third conductive segments and extending from the highest memory routing layer to the next-higher logic routing layer, through the first dielectric layer, the aperture and the second dielectric layer, wherein the conductive via is electrically isolated from the electromagnetic shield.

9. The integrated circuit of claim 6 wherein:

the highest memory routing layer comprises a second conductive segment;

the next-higher logic routing layer comprises a third conductive segment;

the electromagnetic shield comprises an aperture having a side wall;

the integrated circuit further comprises a conductive via which is electrically coupled between the second and third conductive segments and extends from the highest memory routing layer to the next-higher logic routing layer, through the first dielectric layer, wherein the aperture and the second dielectric layer, wherein the conductive via is electrically coupled to the electromagnetic shield at the side wall of the aperture; and

at least one of the second and third conductive segments is electrically coupled to the voltage supply conductor.

10. The integrated circuit of claim 6 and further comprising:

a further memory routing layer fabricated between the first dielectric layer and the embedded memory; and

a third dielectric layer fabricated between the further memory routing layer and the embedded memory.

11. The integrated circuit of claim 6 wherein:

the voltage supply conductor is fabricated in the highest memory routing layer;

the first dielectric layer comprises an aperture with a side wall which extends from the electromagnetic shield to the voltage supply conductor in the highest memory routing layer;

the electromagnetic shield is fabricated on the first dielectric layer and along the side wall of the aperture; and

the integrated circuit further comprises a conductive via which fills the aperture and is electrically coupled to the electromagnetic shield along the side wall of the aperture and is electrically coupled to the voltage supply conductor within the aperture.

12. The integrated circuit of claim 6 wherein:

the voltage supply conductor is fabricated in the next-higher logic routing layer;

the second dielectric layer comprises an aperture which extends from the second conductive segment to the electromagnetic shield; and

the integrated circuit further comprises a conductive via which fills the aperture and is electrically coupled between the voltage supply conductor and the electromagnetic shield.

13. An integrated circuit comprising:

a substrate having a memory area and a non-memory area;

an embedded memory fabricated on the substrate within the memory area;

first and second semiconductor cells fabricated on the substrate within the non-memory area;

a voltage supply conductor;

first, second and third routing layers which are applied over the substrate and are separated from one another by first and second dielectric layers, respectively, wherein the first and second routing layers comprise a plurality of bit lines within the memory area which are electrically coupled to the embedded memory, the second routing layer is a highest memory routing layer relative to the substrate, the third routing layer comprises a signal line which electrically couples the first semiconductor cell to the second semiconductor cell and extends over the memory area, and the third routing layer is the next-higher routing layer on the integrated circuit above the second routing layer and is separated from the second routing layer by the second dielectric layer; and

means for shielding the bit lines within the memory area from an electromagnetic field generated by the signal wire over the memory area, wherein the means for shielding is electrically coupled to the voltage supply conductor.

14. An integrated circuit comprising:

a substrate having a memory area and a non-memory area;

a voltage supply conductor;

an embedded memory fabricated on the substrate within the memory area;

at least one memory routing layer, which includes a highest memory routing layer relative to the substrate, fabricated within the memory area and electrically coupled to the embedded memory;

first and second semiconductor cells fabricated on the substrate within the non-memory area;

an electromagnetic shield fabricated as an additional, non-routing layer on the integrated circuit over the highest memory routing layer and covering substantially the entire memory area, wherein the electromagnetic shield is electrically coupled to the voltage supply conductor;

a logic routing layer, which is the next-higher routing layer on the integrated circuit above the highest memory routing layer and is fabricated over the memory and non-memory areas and over the electromagnetic shield, wherein the logic routing layer has a thickness and the electromagnetic shield has a thickness which is up to one-half of the thickness of the logic routing layer; and

a signal wire electrically coupled between the first and second semiconductor cells and having a first conductive segment routed within the logic routing layer and extending over the memory area.