Non-volatile semiconductor memory device

• US 6,166,407 A
• Filed: 08/24/1998
• Issued: 12/26/2000
• Est. Priority Date: 10/21/1997
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Ohta, Yoshiji
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Wille, Douglas A.
• Application Number:
  US09/138,848
• Time in Patent Office: 855 Days
• Field of Search: 257/71, 257/314, 257/300, 257/298, 257/315, 365/149
• US Class Current: 257/298
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down

Abstract

A non-volatile semiconductor memory device includes: a memory cell section having a plurality of memory cells, each of the memory cells including a flash cell section and a DRAM capacitor section, the flash cell section having at least a drain, a source and a floating gate, the drain being connected to a bit line, the DRAM capacitor section having a capacitive element with two electrodes, one of the electrodes being connected to the source, and the other one of the electrodes being connected to a power supply terminal, and the memory cell being constructed in such a manner that electrons are injected into and extracted from the floating gate at least through the drain by a tunnel current; a register section connected to the memory cell section through the bit line; a bit line selector into which a signal from the bit line is input; and a sensing amplifier for receiving an output from the bit line selector as an input signal. According to the present invention, in the normal operation mode, it is possible to achieve a high-speed random access similar to the one in a general DRAM by reading out or rewriting the volatile data stored in the capacitive element section. On the other hand, in the data retaining mode, final information or invariable information can be stored in the non-volatile memory cell section as non-volatile data.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell section having a plurality of memory cells, each of the memory cells including a flash cell section and a DRAM capacitor section, the flash cell section having at least a drain, a source and a floating gate, the drain being connected to a bit line, the DRAM capacitor section having a capacitive element with two electrodes, one of the electrodes being connected to the source, and the other one of the electrodes being connected to a power supply terminal, and the memory cell being constructed in such a manner that electrons are injected into and extracted from the floating gate at least through the drain by a tunnel current;

a register section connected to the memory cell section through the bit line;

a bit line selector into which a signal from the bit line is input; and

a sensing amplifier for receiving an output from the bit line selector as an input signal.

2. The non-volatile semiconductor memory device of claim 1, further comprising a voltage adjustment circuit for changing an input voltage of the sensing amplifier.

3. The non-volatile semiconductor memory device of claim 1 or 2, wherein the register section comprises a flash cell section and a DRAM capacitor section constituting a memory cell.

4. The non-volatile semiconductor memory device of claim 1 or 2, wherein the register section comprises a DRAM cell including a transistor and a capacitive element, the transistor being formed of a flash cell section without a floating gate.

5. The non-volatile semiconductor memory device of claim 1 or 2, wherein the bit line constitutes one of a pair of complementary bit lines.

6. The non-volatile semiconductor memory device of claim 5, wherein the bit line selector comprises:

a pair of transistors connecting one of the complementary bit lines to a first input terminal of the sensing amplifier and connecting the other one of the complementary bit lines to a second input terminal of the sensing amplifier, and

another pair of transistors connecting the one of the complementary bit lines to the second input terminal of the sensing amplifier and connecting the other one of the complementary bit lines to the first input terminal of the sensing amplifier.

7. The non-volatile semiconductor memory device of claim 2, wherein the voltage adjustment circuit comprises capacitive elements respectively connected to first and second input terminals of the sensing amplifier.