High frequency semiconductor device

• US 6,166,436 A
• Filed: 04/15/1998
• Issued: 12/26/2000
• Est. Priority Date: 04/16/1997
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakamura, Morio, Yoshida, Takayuki, Maeda, Masahiro, Yamazaki, Masazumi
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): LEE, CALVIN
• Application Number:
  US09/060,600
• Time in Patent Office: 986 Days
• Field of Search: 257/728, 257/401, 257/778, 333/247
• US Class Current: 257/723
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01031 : Gallium [Ga]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13064 : High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A high frequency semiconductor device includes: a substrate having a substantially flat principal surface, with a predetermined circuit pattern including at least an input line, an output line, and a ground electrode provided on the principal surface; and a transistor which has a drain electrode, a source electrode, and a gate electrode and is mounted on the substrate by a flip chip mounting. The source electrode and the ground electrode are connected to each other by a first bump in the flip chip mounting.

Claims

1. A high frequency semiconductor device, comprising:

a substrate having a substantially flat principal surface configured for stable and reliable flip chip mounting, with a predetermined circuit pattern including at least an input line, an output line, and a ground electrode provided on the principal surface; and

a transistor which has a drain electrode, a source electrode, and a gate electrode and is mounted on the substrate by a flip chip mounting,

wherein the source electrode and the ground electrode are connected to each other by a first bump in the flip chip mounting, and

a through hole having a conductive pattern on an inside surface thereof, filled with a metal, for supplying a ground potential to the ground electrode is provided in at least in a portion of a region opposing to the drain electrode or the source electrode in the ground electrode.

2. A high frequency semi conductor device according to claim 1,

wherein the transistor further comprises:

a source electrode pad which is electrically connected to the source electrode by a source extension line; and

a gate electrode pad which is electrically connected to the gate electrode by a gate extension line,

and wherein a width of the source extension line at an overlapped area of the source extension line and the gate extension line is smaller than a width of the source electrode.

3. A high frequency semiconductor device according to claim 1, wherein each of the drain electrode and the gate electrode comprise a first region and a second region, wherein at least one of said first and second regions do not oppose the around electrode.

4. A high frequency semiconductor device according to claim 1, wherein the transistor comprises a first region and a second region, wherein said second region does not oppose the ground electrode;

and at least one of the drain electrode and the gate electrode is formed only in the second region.

5. A high frequency semiconductor device according to claim 4, wherein both of the drain electrode and the gate electrode are formed only in the second region of the transistor.

6. A high frequency semiconductor device according to claim 4, wherein the ground electrode has a comb-shaped pattern.

7. A high frequency semiconductor device according to claim 4, wherein the ground electrode has an island-shaped pattern.

8. A high frequency semiconductor device according to claim 1, wherein:

the ground electrode is formed in a band shape;

the transistor further includes a source electrode pad which is electrically connected to the source electrode by a source extension line and a gate electrode pad which is electrically connected to the gate electrode by a gate extension line; and

a width of the ground electrode is smaller than a distance between the drain extension line and the gate extension line.

9. A high frequency semiconductor device according to claim 1, wherein the first bump has a layered structure including a lower bump layer and an upper bump layer provided on the lower bump layer;

and a hardness of the lower bump layer is different from a hardness of the upper bump layer, such that a ratio of Vickers hardness of the lower bump layer to Vickers hardness of the upper bump layer is greater than about 3, which provides a suppression in a variation of a threshold voltage.

10. A high frequency semiconductor device according to claim 1, wherein the first bump has a cross section of a substantially n-sided shape (where n is an integer equal to or greater than 4).

11. A high frequency semiconductor device according to claim 1, wherein a plurality of the first bumps are provided;

and each of the plurality of the first bumps has substantially the same size.

12. A high frequency semiconductor device according to claim 1, further comprising a second bump for electrically connecting at least one of the gate electrode and the drain electrode to the circuit pattern on the substrate, wherein the second bump has substantially the same size as the first bump.

13. A high frequency semiconductor device according to claim 12, wherein a plurality of the first bumps and a plurality of the second bumps are provided;

and each of the plurality of the first bumps and the plurality of the second bumps has substantially the same size.

14. A high frequency semiconductor device according to claim 1, wherein the flip chip mounting is performed by a microbump bonding method, wherein the parasitic inductance caused by the first bump is substantially suppressed.

15. A high frequency semiconductor device according to claim 1, wherein the substrate is a (100) substrate;

and the transistor is mounted on the substrate so that a longitudinal direction of the gate electrode is substantially parallel to a {010} direction of the substrate.

16. A high frequency semiconductor device according to claim 1, wherein the substrate is a (100) substrate;

and the transistor is mounted on the substrate so that a longitudinal direction of the gate electrode is substantially parallel to a {001} direction of the substrate.

17. A high frequency semiconductor device, comprising:

a substrate having a substantially flat principal surface, with a predetermined circuit pattern including at least an input line, an output line, and a ground electrode provided on the principal surface; and

a transistor which has a drain electrode, a source electrode, and a gate electrode and is mounted on the substrate by a flip chip mounting,

wherein the source electrode and the ground electrode are connected to each other by a first bump in the flip chip mounting,

wherein the transistor further comprises;

a source electrode pad which is electrically connected to the source electrode by a source extension line, and

a gate electrode pad which is electrically connected to the gate electrode by a gate extension line,

and wherein a width of the source extension line at an overlapped area of the source extension line and the gate extension line is smaller than a width of the source electrode, and

wherein a ratio of the width of the source extension line at the overlapped area of the source extension line and the gate extension line to the width of the source electrode is in the range of up to 0.5.