Method and apparatus for dual mode output buffer impedance compensation
First Claim
1. A method of programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength, the method comprising:
- coupling a test resistor between a source of the second signaling level and a mode terminal;
sensing a first level at the mode terminal;
uncoupling the test resistor from the mode terminal;
if the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal;
otherwise,programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal.
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Abstract
A method and circuit for programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength. The method includes coupling a test resistor between a source of the second signaling level and a mode terminal, sensing a first level at the mode terminal, and uncoupling the test resistor from the mode terminal. If the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal. Otherwise, programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal. The circuit includes a first counter coupled to the first comparator to produce a first value responsive to the mode flag, the mode terminal, and the reference level. A first latch, coupled to the first counter, provides the adjusted first value to the first output driver. A second latch, coupled to the second counter, provides the adjusted second value to the second output driver.
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Citations
21 Claims
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1. A method of programming an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength, the method comprising:
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coupling a test resistor between a source of the second signaling level and a mode terminal; sensing a first level at the mode terminal; uncoupling the test resistor from the mode terminal; if the first level is between the second signaling level and a reference level, then programming the output buffer with reference to an unterminated transmission line coupled to the mode terminal;
otherwise,programming the output buffer with reference to an external resistor coupled between a source of the first signaling level and the mode terminal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A compensation circuit for an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength, the compensation circuit comprising:
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a mode terminal; a test resistor switchably coupled to the mode terminal; a first comparator coupled to the mode terminal to compare a first level at the mode terminal to a reference level; a mode flag coupled to the first comparator such that, if the first level is between the second signaling level and the reference level, the mode flag is set to indicate that an unterminated transmission line is coupled to the mode terminal, otherwise, the mode flag is set to indicate that an external resistor is coupled between a source of the first signaling level and the mode terminal; a first counter coupled to the first comparator, said first counter to produce a first value responsive to the mode flag, the mode terminal, and the reference level; a first latch, coupled to the first counter and the first output driver, such that the adjusted first value is provided to the first output driver; a second counter coupled to the first comparator, said second counter to produce a second value responsive to the mode flag, the mode terminal, and the reference level; a second latch, coupled to the second counter and the second output driver, such that the adjusted second value is provided to the second output driver. - View Dependent Claims (14, 15, 16, 17)
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18. A data transmission system with impedance compensation comprising:
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an output buffer having a first output driver for producing a first signaling level with a first programmable strength and a second output driver for producing a second signaling level with a second programmable strength; a differential line receiver coupled to the output of the output buffer and a reference level; a compensation circuit coupled to the output buffer to program the first and second programmable strengths, said compensation circuit further having a mode terminal; a test resistor switchably coupled to the mode terminal; a first comparator coupled to the mode terminal to compare a first level at the mode terminal to a reference level; a mode flag coupled to the first comparator such that, if the first level is between the second signaling level and the reference level, the mode flag is set to indicate that an unterminated transmission line is coupled to the mode terminal, otherwise, the mode flag is set to indicate that an external resistor is coupled between a source of the first signaling level and the mode terminal; a first counter coupled to the first comparator, said first counter to produce a first value responsive to the mode flag, the mode terminal, and the reference level; a first latch, coupled to the first counter and the first output driver, such that the adjusted first value is provided to the first output driver; a second counter coupled to the first comparator, said second counter to produce a second value responsive to the mode flag, the mode terminal, and the reference level; a second latch, coupled to the second counter and the second output driver, such that the adjusted second value is provided to the second output driver. - View Dependent Claims (19, 20, 21)
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Specification