Voltage-controlled delay line, direct phase controlled voltage-controlled oscillator, clock/data recovery circuit, and clock/data recovery apparatus
First Claim
1. A voltage-controlled delay line for delaying an externally generated input clock signal according to a control voltage signal and a phase selection signal, comprising:
- a first cascaded series of first logic gates with voltage-controlled propagation delays, the propagation delays of said first logic gates being controlled in common by said control voltage signal; and
a plurality of second logic gates receiving said input clock signal, one second logic gate being coupled to every M-th first logic gate in said first cascaded series, M being a positive integer, each of said second logic gates being independently controllable by said phase selection signal, said input clock signal being supplied to one of said first logic gates through one of said second logic gates, as selected by said phase selection signal, and output as a delayed clock signal from a last one of said first logic gates in said first cascaded series.
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Abstract
A clock/data recovery device employs a phase-locked loop that supplies a single clock signal and a control voltage signal to at least one clock/data recovery circuit. The clock/data recovery circuit has a voltage-controlled delay line or direct phase controlled voltage-controlled oscillator that generates a multiple-phase clock signal, which is used to recover a clock signal and data from a received data signal. The voltage-controlled delay line or direct phase controlled vottage-controlled oscillator has a cascade or ring of voltage controlled logic gates, with propagation delays controlled by the control voltage signal from the phase-locked loop, and additional logic gates that supply the clock signal from the phase-locked loop to a selectable one of the voltage-controlled logic gates.
122 Citations
29 Claims
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1. A voltage-controlled delay line for delaying an externally generated input clock signal according to a control voltage signal and a phase selection signal, comprising:
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a first cascaded series of first logic gates with voltage-controlled propagation delays, the propagation delays of said first logic gates being controlled in common by said control voltage signal; and a plurality of second logic gates receiving said input clock signal, one second logic gate being coupled to every M-th first logic gate in said first cascaded series, M being a positive integer, each of said second logic gates being independently controllable by said phase selection signal, said input clock signal being supplied to one of said first logic gates through one of said second logic gates, as selected by said phase selection signal, and output as a delayed clock signal from a last one of said first logic gates in said first cascaded series. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A direct phase controlled voltage-controlled oscillator receiving an externally generated input clock signal, a control voltage signal, and a phase selection signal, comprising:
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a plurality of first logic gates with voltage-controlled propagation delays, said first logic gates being coupled in a ring, the propagation delays of said first logic gates being controlled in common by said control voltage signal; and a plurality of second logic gates coupled to respective first logic gates, each of said second logic gates being independently controllable by said phase selection signal, said input clock signal being supplied to one of said first logic gates through one of said second logic gates, as selected by said phase selection signal. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification