Semiconductor test structure formed in cutting path of semiconductor water

• US 6,166,607 A
• Filed: 03/05/1999
• Issued: 12/26/2000
• Est. Priority Date: 03/05/1998
• Status: Expired due to Term

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Schoellkopf, Jean-Pierre
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/264,150
• Time in Patent Office: 662 Days
• Field of Search: 331/57, 324/763, 324/765, 438/18
• US Class Current: 331/57
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A semiconductor test structure includes a semiconductor test device having at least one group of test cells that are connected in series and looped back so as to form an oscillator. Each test cell includes a base cell that is formed at least partially in the semiconductor substrate and an ancillary structure that is connected to at least one of the terminals of the base cell. Further, the ancillary structure is distributed over at least two metallization levels that are above the base cell, and is formed on each metallization level by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

Claims

1. In a semiconductor test structure of the type formed in a cutting path of a semiconductor substrate wafer, a semiconductor test device comprising:

at least one group of test cells that are connected in series and looped back so as to form an oscillator, each of the test cells including;

a base cell formed at least partially in the semiconductor substrate, the base cell including a set of terminals; and

an ancillary structure connected to at least one of the terminals of the base cell,

wherein the ancillary structure is distributed over at least first and second metallization levels that are above the base cell, and is formed on each of the metallization levels by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

2. The semiconductor test device as defined in claim 1, wherein on each of the metallization levels, the first network of metal tracks of the ancillary structure is connected to ground and the second network of metal tracks of the ancillary structure is connected to only one of an input terminal and an output terminal of the base cell, so as to form a capacitive ancillary structure.

3. The semiconductor test device as defined in claim 2, wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs.

4. The semiconductor test device as defined in claim 3, wherein the first and second networks of metal tracks of the second metallization level form two mutually imbricated combs.

5. The semiconductor test device as defined in claim 2, wherein the general orientation of the first network of the first metallization level is different than the general orientation of the first network of the second metallization level.

6. The semiconductor test device as defined in claim 1,

wherein on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to ground, and

the ancillary structure includes interconnection vias that successively connect an output terminal of the base cell, the second network of the first metallization level of the ancillary structure, the second network of the second metallization level of the ancillary structure, the second network of a third metallization level of the ancillary structure, and the second network of a fourth metallization level.

7. The semiconductor test device as defined in claim 6, wherein the second network of the fourth metallization level is electrically connected to an input terminal of the base cell of the next test cell so as to form a resistive and capacitive ancillary structure that has a continuous electrical pathway between the output terminal of the base cell and the input terminal of the base cell of the next test cell.

8. The semiconductor test device as defined in claim 6, wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs.

9. An oscillator comprising a plurality of test cells that are connected in series and looped back, at least one of the test cells comprising:

a base cell having an input terminal and an output terminal; and

an ancillary structure connected to at least one of the input terminal and the output terminal of the base cell,

wherein the ancillary structure is distributed over at least first and second metallization levels, and

the ancillary structure is formed on each of the metallization levels by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form a capacitive ancillary structure.

10. The oscillator as defined in claim 9, wherein the base cell includes an inverter.

11. The oscillator as defined in claim 9, wherein the first and second metallization levels are above the base cell.

12. The oscillator as defined in claim 9, wherein on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to a ground terminal and the second network of metal tracks of the ancillary structure is electrically connected to only one of the input terminal and the output terminal of the base cell, so as to form a capacitive ancillary structure.

13. The oscillator as defined in claim 12,

wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs, and

the first and second networks of metal tracks of the second metallization level form two mutually imbricated combs.

14. The oscillator as defined in claim 12, wherein the general orientation of the first network of the first metallization level is different than the general orientation of the first network of the second metallization level.

15. The oscillator as defined in claim 9,

wherein on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to a ground terminal, and

the ancillary structure includes interconnection vias that successively connect the output terminal of the base cell of the at least one test cell, the second network of the first metallization level of the ancillary structure, the second network of the second metallization level of the ancillary structure, the second network of a third metallization level of the ancillary structure, and the second network of a fourth metallization level.

16. The oscillator as defined in claim 15, wherein the second network of the fourth metallization level is electrically connected to an input terminal of the base cell of a test cell following the at least one test cell, so as to form a resistive and capacitive ancillary structure that has a continuous electrical pathway between the output terminal of the base cell of the at least one test cell and the input terminal of the base cell of the test cell following the at least one test cell.

17. The oscillator as defined in claim 15, wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs.

18. A semiconductor test structure comprising:

a first test device having at least one oscillator formed solely of base cells; and

a second test device having at least one oscillator formed of at least one group of test cells that are connected in series and looped back so as to form an oscillator, each of the test cells including;

a base cell formed at least partially in the semiconductor substrate; and

an ancillary structure connected to at least one of the terminals of the base cell,

wherein the ancillary structure is distributed over at least first and second metallization levels that are above the base cell, and is formed on each of the metallization levels by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure.

19. The semiconductor test structure as defined in claim 18, wherein on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to ground and the second network of metal tracks of the ancillary structure is electrically connected to only one of an input terminal and an output terminal of the base cell, so as to form a capacitive ancillary structure.

20. The semiconductor test structure as defined in claim 19,

wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs, and

the first and second networks of metal tracks of the second metallization level form two mutually imbricated combs.

21. The semiconductor test structure as defined in claim 19, wherein the general orientation of the first network of the first metallization level is different than the general orientation of the first network of the second metallization level.

22. The semiconductor test structure as defined in claim 19, further comprising a third test device having at least one oscillator formed of at least one group of test cells that are connected in series and looped back so as to form an oscillator, each of the test cells of the third test device including:

a base cell formed at least partially in the semiconductor substrate; and

an ancillary structure connected to at least one of the terminals of the base cell,

wherein the ancillary structure is distributed over at least first and second metallization levels that are above the base cell, and is formed on each of the metallization levels by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure,

on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to ground, and

the ancillary structure includes interconnection vias that successively connect an output terminal of the base cell, the second network of the first metallization level of the ancillary structure, the second network of the second metallization level of the ancillary structure, the second network of a third metallization level of the ancillary structure, and the second network of a fourth metallization level.

23. A semiconductor test structure comprising:

a first test device having at least one oscillator formed solely of base cells; and

a second test device having at least one oscillator formed of at least one group of test cells that are connected in series and looped back so as to form an oscillator, each of the test cells including;

a base cell formed at least partially in the semiconductor substrate; and

an ancillary structure connected to at least one of the terminals of the base cell,

wherein the ancillary structure is distributed over at least first and second metallization levels that are above the base cell, and is formed on each of the metallization levels by first and second mutually entangled networks of metal tracks that are electrically arranged so as to form an at least capacitive ancillary structure,

on each of the metallization levels, the first network of metal tracks of the ancillary structure is electrically connected to ground, and

the ancillary structure includes interconnection vias that successively connect an output terminal of the base cell, the second network of the first metallization level of the ancillary structure, the second network of the second metallization level of the ancillary structure, the second network of a third metallization level of the ancillary structure, and the second network of a fourth metallization level.

24. The semiconductor test structure as defined in claim 23, wherein the second network of the fourth metallization level is electrically connected to an input terminal of the base cell of the next test cell so as to form a resistive and capacitive ancillary structure that has a continuous electrical pathway between the output terminal of the base cell and the input terminal of the base cell of the next test cell.

25. The semiconductor test structure as defined in claim 23, wherein the first and second networks of metal tracks of the first metallization level form two mutually imbricated combs.