Method and apparatus for providing DC offset correction and hold capability

• US 6,166,668 A
• Filed: 06/01/1999
• Issued: 12/26/2000
• Est. Priority Date: 06/01/1999
• Status: Expired due to Term

• Current Assignee: Motorola Solutions, Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Bastani, Babak, Heck, Joseph P., Bautista, Edwin E.
• Primary Examiner(s): YOUNG, BRIAN K
• Application Number:
  US09/323,376
• Time in Patent Office: 574 Days
• Field of Search: 341/118, 341/155
• US Class Current: 341/118
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

A direct current (DC) offset correction loop (200) for determining the required amount of DC offset to an analog input signal includes a digital integrator (211) for measuring the amount of DC offset present at the final output of a forward signal path and a hold circuit (213) for controlling the digital integrator (213). The DC offset correction loop (200) provides a constant amount of DC offset correction to the analog input signal.

Claims

1. A direct current (DC) offset correction loop removing unwanted DC offset from an analog input signal comprising:

at least one baseband filter for filtering unwanted signal components from the analog input signal waveform;

at least one digital integrator for extracting any amount of DC offset present at the final output of the forward signal path; and

a hold circuit for controlling the digital integrator for providing a constant amount of DC offset correction to the analog input signal.

2. A DC offset correction loop as in claim 1, further comprising:

at least one gain amplifier for amplifying the output of the at least one baseband filter.

3. A DC offset correction loop as in claim 1, further comprising:

control logic for providing a predetermined digital signal based on information from the at least one digital integrator.

4. A DC offset correction loop as in claim 1, further comprising:

a digital to analog converter for converting a digital DC offset correction from the at least one digital integrator to correct the DC offset of the analog input signal.

5. A DC offset correction loop as in claim 1, wherein:

the hold circuit includes a plurality of switches for controlling the input to the at least one digital integrator.

6. HA direct current (DC) offset correction loop comprising:

at least one analog baseband filter for filtering preselected signal components from an analog input signal having a DC offset;

an analog to digital converter (ADC) for converting the signal from the at least one analog baseband filter to a digital signal;

a digital integrator for extracting the DC offset of the digital signal and providing a predetermined amount of DC offset correction;

control logic for converting the predetermined amount of DC offset correction into a predetermine digital format; and

a digital to analog converter (DAC) for converting the predetermined digital format into a analog signal for offsetting the DC offset of the analog input signal.

7. A DC offset correction loop as in claim 6, further comprising:

a hold controller for controlling the input of the digital integrator and providing a predetermined amount of DC offset correction to the analog input signal.

8. A DC offset correction loop as in claim 7, wherein:

the hold controller is comprised of at least one switch.

9. A DC offset correction loop as in claim 8 wherein the at least one switch is comprised of a plurality of logic devices.

10. A DC offset correction loop as in claim 6, further comprising;

at least one amplifier for amplifying the output of the at least one analog baseband filter.

11. A DC offset correction loop as in claim 6, wherein:

the digital integrator includes at least one adder and at least one first delay circuit.

12. A DC offset correction loop as in claim 6, wherein:

the ADC converts the analog signal to a multi-bit digital signal having desired resolution.

13. A DC offset correction loop as in claim 6, wherein:

the at least one digital integrator produces a multi-bit signal.

14. A DC offset correction loop as in claim 6, wherein the control logic produces two digital signals from the at least one digital integrator.

15. A DC offset correction loop as in claim 6, wherein the DC offset correction is applied to the at least one analog baseband filter.

16. A DC offset correction loop as in claim 6, further comprising:

a second delay circuit for delaying the output of the analog-to-digital converter; and

a digital subtractor for providing a digital control signal to the control logic based on the delayed output.

17. A DC offset correction loop as in claim 10, wherein the digital control signal provides a fine DC offset adjustment.

18. A direct current (DC) offset correction loop comprising:

at least one analog baseband filter for filtering preselected signal components from analog input signal having a DC offset;

an analog to digital converter (ADC) for converting the signal from the at least one analog baseband filter to a digital signal;

a digital integrator for extracting the DC offset of the digital signal and providing a predetermined amount of DC offset correction;

control logic for converting the predetermined amount of DC offset correction into a predetermine digital format;

a digital to analog converter (DAC) for converting the predetermined digital format into a analog signal for offsetting the DC offset of the analog input signal; and

a digital subtractor for providing a control signal to the control logic.

19. A DC offset correction loop as in claim 18, further comprising:

a hold controller for controlling the input of the digital integrator and providing a predetermined amount of DC offset correction to the analog input signal.

20. A DC offset correction loop as in claim 19, wherein:

the hold controller is comprised of at least one switch.

21. A DC offset correction loop as in claim 20 wherein the at least one switch is comprised of a plurality of logic devices.

22. A DC offset correction loop as in claim 18, further comprising;

at least one amplifier for amplifying the output of the at least one analog baseband filter.

23. A DC offset correction loop as in claim 18, wherein:

the digital integrator includes at least one adder and at least one first delay circuit.

24. A DC offset correction loop as in claim 18, wherein:

the ADC converts the analog signal to a multi-bit digital signal having desired resolution.

25. A DC offset correction loop as in claim 18, wherein:

the at least one digital integrator produces a multi-bit signal.

26. A DC offset correction loop as in claim 18, wherein the control logic produces two digital signals from the at least one digital integrator.

27. A DC offset correction loop as in claim 18, wherein the DC offset correction is applied to the at least one analog baseband filter.

28. A DC offset correction loop as in claim 18, wherein the digital subtractor receives a delayed digital signal from the ADC.

29. A DC offset correction loop as in claim 28, wherein the control signal is a substantially fine adjustment for DC offset error correction.

30. A method for providing direct current (DC) offset comprising the steps of:

filtering an analog input signal having a DC offset with at least one baseband filter to remove unwanted signal components;

converting the filtered analog signal to a digital signal with an analog-to-digital converter (ADC);

integrating the digital signal from the ADC using a digital integrator for extracting undesired DC offset;

converting the extracted DC offset into an analog DC correction signal;

applying the analog DC correction signal to that at least one portion of the forward signal path filter for eliminating the DC offset at the final output of the forward signal path.

31. A method for providing DC offset as in claim 30, further comprising the step of:

holding the level of DC offset correction by controlling the digital integrator.

32. A method for providing DC offset as in claim 30, further comprising the step of:

grounding an input to the digital integrator for holding a level of DC offset correction applied to the analog input signal.

33. A method for providing DC offset as in claim 30, further comprising the step of:

amplifying the output of the at least one baseband filter for input to the ADC.