Multi title-configured phased array antenna architecture

• US 6,166,705 A
• Filed: 07/20/1999
• Issued: 12/26/2000
• Est. Priority Date: 07/20/1999
• Status: Expired due to Term

• Current Assignee: North South Holdings Incorporated (Spherix Incorporated)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Mast, Alan W., Shipley, John W., Heckaman, Douglas E., Whybrew, Walter M.
• Primary Examiner(s): Ho, Tan
• Application Number:
  US09/357,680
• Time in Patent Office: 525 Days
• Field of Search: 343/700 MS, 343/850, 343/853, 343/909, 343/893, 342/361, 342/368, 342/372, 342/375
• US Class Current: 343/853
• CPC Class Codes: H01Q 1/38 formed by a conductive layer on an insulating support patch antennas H01Q9/0407; microstrip dipole antennas H01Q9/065; microstrip slot antennas H01Q13/106; transmission line microstrip antennas H01Q13/206; manufacturing reflecting surfaces using insulating material for supporting the reflecting surface H01Q15/142
• CPC Class Codes: H01Q 21/0025 Modular arrays
• CPC Class Codes: H01Q 21/065 Patch antenna array

Abstract

A multi-tile configured, two-dimensional phased array antenna architecture is configured of an gridwork of sub-array `tiles`, each of which contains a mechanically integrated and RF-integrated antenna elements and RF interface components therefor. Each tile is formed of a multilayer printed wiring board and supports a sub-array of antenna elements and their associated RF circuits, so that the tile itself is effectively an operative phased-array antenna. The gridwork supports the sub-array tiles in sealed engagement with the framework, whereby associated RF networks components at rear sides of the tiles are protected against the free space environment to which the antenna elements on front faces of the tiles are exposed. Each RF interface network contains signal processing circuitry for controlling the operation of a respective one or a set of the antenna elements on the front side of the tile.

Claims

1. A phased array antenna architecture comprising:

a plurality of phased array antenna tiles, a respective phased array antenna tile including

a multilayer printed circuit wiring board containing a laminate of interconnect layers, including control signal and DC voltage distribution conductors that provide control signal interconnectivity and DC power distribution for antenna and RF signal processing circuit devices of said respective phased array antenna tile, interposed between first and second opposite sides of said multilayer printed circuit wiring board,

a plurality of signal processing interface networks including RF microstrip networks distributed on said first side of said multilayer printed circuit wiring board,

a plurality of RF signal processing circuit devices mounted to and connected by said plurality of signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board to said control signal and DC voltage distribution conductors of said laminate of interconnect layers, and

a plurality of antenna elements distributed over said second side of said multilayer printed circuit wiring board, and being coupled through said multilayer printed circuit wiring board to associated ones of said plurality of RF signal processing circuit devices mounted to said signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board; and

a support structure for supporting said plurality of phased array antenna tiles.

2. A phased array antenna architecture according to claim 1, wherein said support structure is configured to support said plurality of phased array antenna tiles in an array configuration, and such that said signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board are effectively protected from the environment to which said plurality of antenna elements are exposed.

3. A phased array antenna architecture according to claim 1, further including signal processing interface networks distributed on said second side of said multilayer printed circuit wiring board.

4. A phased array antenna architecture according to claim 1, further including at least one power and control unit supported at first sides of multilayer printed circuit wiring boards of said plurality of phased array antenna tiles, and being operative to supply power to and control the operation of said plurality of phased array antenna tiles.

5. A phased array antenna architecture according to claim 4, wherein said at least one power and control unit is operative to supply power, control signals and RF signals to said tiles.

6. A phased array antenna architecture according to claim 5, wherein said at least one power and control unit is operative to supply said power, control signals and RF signals over a common transmission link, and wherein said plurality of signal processing interface networks are configured to filter out and supply said power, control signals and RF signals to said tiles.

7. A phased array antenna architecture according to claim 1, wherein said laminate of interconnect layers interposed between first and second opposite sides of said multilayer printed circuit wiring board includes RF distribution networks and filtering conductive patterns.

8. A phased array antenna architecture according to claim 1, wherein said RF signal processing circuit devices include unpackaged semiconductor circuit die surface-mounted to said plurality of signal processing interface networks distributed on said first side of said printed wiring board.

9. A phased array antenna architecture according to claim 1, wherein said RF signal processing circuit devices include unpackaged semiconductor circuit die having wire-bond connections to said plurality of signal processing interface networks distributed on said first side of said printed wiring board.

10. A phased array antenna architecture according to claim 1, wherein a respective one of said plurality of antenna elements distributed on said second side of said multilayer printed circuit wiring board is coupled by means of a plated via through said multilayer printed circuit wiring board to an associated RF signal processing circuit device on said first side of said multilayer printed circuit wiring board.

11. A phased array antenna architecture according to claim 1, wherein a respective one of said plurality of antenna elements distributed on said second side of said multilayer printed circuit wiring board is coupled by means of a glass-surrounded conductor passing through an aperture in said multilayer printed circuit wiring board to an associated RF signal processing circuit device on said first side of said multilayer printed circuit wiring board.

12. A phased array antenna architecture comprising an array of antenna sub-array tiles supported by a grid-configured support structure, a respective sub-array tile containing a multilayer printed circuit wiring board having a laminate of interconnect layers, including control signal and DC voltage distribution conductors that provide control signal interconnectivity and DC power distribution for antenna and RF signal processing circuit devices of said respective sub-array tile, interposed between first and second opposite sides of said board, a plurality of signal processing interface networks, including RF microstrip networks, distributed on said first side of said multilayer printed circuit wiring board, a plurality of RF signal processing circuit devices mounted to and connected by said plurality of signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board to said control signal and DC voltage distribution conductors of said laminate of interconnect layers, and a plurality of antenna elements distributed over said second side of said multilayer printed circuit wiring board, and coupled through said multilayer printed circuit wiring board to associated ones of RF signal processing circuit devices mounted to said plurality of RF signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board.

13. A phased array antenna architecture according to claim 12, further including power supply and control units coupled with said multilayer printed circuit wiring boards, and being operative to supply power to, interface RF signalling with, and control the operation of said tiles.

14. A phased array antenna architecture according to claim 12, wherein a respective one of said plurality of antenna elements distributed on said second side of said multilayer printed circuit wiring board is coupled by means of a plated via through said multilayer printed circuit wiring board to an associated RF signal processing circuit device on said first side of said multilayer printed circuit wiring board.

15. A phased array antenna architecture according to claim 12, wherein a respective one of said plurality of antenna elements distributed on said second side of said multilayer printed circuit wiring board is coupled by means of a glass-surrounded conductor passing through an aperture in said multilayer printed circuit wiring board to an associated RF signal processing circuit device on said first side of said multilayer printed circuit wiring board.

16. A phased array antenna architecture according to claim 12, further including signal processing interface networks distributed on said second side of said multilayer printed circuit wiring boards.

17. A phased array antenna architecture according to claim 12, further including at least one power and control unit supported at first sides of said multilayer printed circuit wiring boards, and being operative to supply power, control signals and RF signals to said tiles.

18. A phased array antenna architecture according to claim 17, wherein said at least one power and control unit is operative to supply said power, control signals and RF signals over a common transmission link, and wherein said plurality of signal processing interface networks are configured to filter out and supply said power, control signals and RF signals to said tiles.

19. A method of configuring a phased array antenna comprising the steps of:

(a) providing a plurality of phased array antenna tiles, a respective phased array antenna tile including a multilayer printed circuit wiring board containing a laminate of interconnect layers, including control signal and DC voltage distribution conductors that provide control signal interconnectivity and DC power distribution for antenna and signal processing circuit devices of said respective phased array antenna tile, interposed between first and second opposite sides thereof, RF signal processing interface networks including RF microstrip networks distributed on said first side of said multilayer printed circuit wiring board, a plurality of RF signal processing circuit devices mounted to and connected by said plurality of RF signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board to said control signal and DC voltage distribution conductors of said laminate of interconnect layers, and a plurality of antenna elements distributed over said second side of said multilayer printed circuit wiring board, and being coupled through said multilayer printed circuit wiring board to associated ones of said plurality of RF signal processing circuit devices mounted to said RF signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board; and

(b) attaching said phased array antenna tiles to a grid-configured support structure therefor.

20. A method according to claim 19, wherein step (b) comprises attaching said phased array antenna tiles to a grid-configured support structure that is configured to support said plurality of phased array antenna tiles in an array configuration, and such that said signal processing interface networks distributed on said first side of said multilayer printed circuit wiring board are effectively protected from the environment to which said plurality of antenna elements are exposed.

21. A method according to claim 20, further including the step of:

(c) mounting at least one power and control unit at first sides of said multilayer printed circuit wiring boards, and coupling said at least one power and control unit to multiple ones of said tiles so as to supply power to and control the operation thereof.