Thin film transistor and fabricating method thereof having patterned active layer

• US 6,166,785 A
• Filed: 10/01/1999
• Issued: 12/26/2000
• Est. Priority Date: 10/02/1998
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Ha, Yong Min
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): QI, ZHI QIANG
• Application Number:
  US09/410,097
• Time in Patent Office: 452 Days
• Field of Search: 349/42, 349/41, 349/43, 349/47, 257/59, 257/72, 438/30, 438/164, 438/299
• US Class Current: 349/42
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

The present invention relates to a thin film transistor and a fabricating method thereof which is applied to a buried bus coplanar type TFT wherein the source and drain wires are located on a substrate. The present invention includes an insulated substrate, a source electrode and a drain electrode on the insulated substrate, a first insulating layer on the insulated substrate wherein the first insulating layer has a predetermined pattern, an active layer on the first insulating layer wherein the active layer has a source region, a channel region and a drain region, a second insulating layer covering the active layer, and a gate electrode on the second insulating layer over the channel region.

Claims

1. A method of fabricating a thin film transistor, comprising the steps of:

forming a source electrode and a drain electrode on a substrate;

depositing a first insulating layer on an surface of the substrate including the source and drain electrodes;

forming a patterned active layer on the first insulating layer;

exposing the source and drain electrodes by etching the first insulating layer using the patterned active layer as a mask;

depositing a second insulating layer covering an exposed surface of the substrate including the active layer and the source and drain electrodes;

forming a gate electrode on the second insulating layer over the active layer; and

forming a source region and a drain region by doping the active layer using the gate electrode as a mask.

2. The method of claim 1, wherein the active layer is formed with polycrystalline silicon.

3. The method of claim 1, the method further comprising the steps of:

depositing a third insulating layer covering the gate electrode and an exposed surface of the substrate;

forming contact holes exposing the source and drain electrodes and the source and drain regions by etching the third and second insulating layers; and

forming a first wire connecting the source electrode to the source region and a second wire connecting the drain electrode to the drain region.

4. The method of claim 3, wherein contact holes exposing the source and drain electrodes and the source and drain regions are formed in the third insulating layer.

5. The method of claim 3, wherein the third insulating layer is formed with one of a silicon oxide layer, a silicon nitride layer, a stacked layer of silicon oxide and silicon nitride and an organic insulating layer.

6. The method of claim 1, wherein each one of the source and drain electrodes is comprised of double layers.

7. The method of claim 6, wherein the source and drain electrodes are formed by depositing successively a first conductive layer and a second conductive layer on the insulated substrate and by etching the first and second conductive layers simultaneously using a single mask.

8. The method of claim 6, wherein the source and drain electrodes are formed by depositing successively a first conductive layer and a second conductive layer on the insulated substrate and by etching the first and second conductive layers in turn using a single mask.

9. The method of claim 6, wherein the source and drain electrodes are formed by depositing and etching a first conductive layer on the insulated substrate, by deposing a second conductive layer covering the first conductive layer by etching the second conductive layer by photolithography.

10. The method of claim 6, wherein the source and drain electrodes are formed by depositing and etching a first conductive layer on the insulated substrate, by deposing a second conductive layer covering the first conductive layer by etching the second conductive layer by photolithography.

11. The method of claim 1, wherein the first insulating layer is formed to be about 3000-10000 Å

thick.

12. The method of claim 1, wherein the patterned active layer is covered by photoresist during the exposing step.

13. The method of claim 1, wherein the patterned active layer is uncovered during the exposing step.

14. A method of fabricating a liquid crystal display, comprising the steps of:

forming a data line having a source electrode on a substrate;

depositing a first insulating layer on an exposed surface of the substrate including the data line;

depositing an amorphous silicon layer on the first insulating layer;

forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer;

forming an active layer by patterning the polycrystalline silicon layer;

exposing the data line by etching the first insulating layer using the active layer as a mask;

depositing a second insulating layer on an exposed surface of the substrate including the active layer and the data line;

forming a gate line on the insulating layer over the active layer wherein the gate line having a gate electrode and the data line cross each other;

forming a source region and a drain region in the active layer by doping the active layer with impurities in use of the gate electrode as a mask;

depositing a third insulating layer covering an exposed surface of the substrate including the gate line;

forming contact holes exposing the source electrode and the source and drain regions in the second and third insulating layers; and

forming an interconnection wire connecting the source electrode to the source region and a pixel electrode connected to the drain region.

15. The method of claim 14, the method further comprising the step of forming a first capacitor electrode for a storage capacitor by overlapping a portion of the pixel electrode with another portion of the third insulating layer.

16. The method of claim 14, wherein a plurality of insertion layers lying at a first position where the gate line and the data line cross each other and at a second position where the first capacitor electrode and the data line cross each other are formed by etching the polycrystalline layer by photolithography as well as the active layer simultaneously.

17. The method of claim 16, wherein the first insulating layer is etched using the insertion layers and the active layer as masks.

18. The method of claim 14, wherein the polycrystalline silicon layer is patterned by photolithography.

19. The method of claim 14, wherein the active layer is covered by photoresist during the exposing step.

20. The method of claim 14, wherein the active layer is uncovered during the exposing step.