Self calibrating pulse width modulator for use in electrostatic printing applications

• US 6,166,821 A
• Filed: 10/02/1998
• Issued: 12/26/2000
• Est. Priority Date: 10/02/1998
• Status: Expired due to Term

• Current Assignee: Electronics For Imaging Incorporated
• Original Assignee: Electronics For Imaging Incorporated
• Inventors: Blumer, Marc
• Primary Examiner(s): Coles, Edward L.
• Assistant Examiner(s): WALLERSON, MARK E
• Application Number:
  US09/165,749
• Time in Patent Office: 816 Days
• Field of Search: 358/1.1, 358/1.2, 358/1.3, 358/1.4, 358/1.7, 358/1.8, 358/296, 358/298, 347/5, 347/10, 347/11, 347/112-117, 347/128-144, 399/128, 399/167
• US Class Current: 358/1.1
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H04N 1/4056 the pattern varying in one dimension only, e.g. dash length, pulse width modulation [PWM]

Abstract

An arrangement for producing a variable width pulse is disclosed for use in an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on predetermined digital data. The variable width pulse is formed during a clock interval which is established by a clock signal such that the width of the pulse during the clock interval is based on the digital data and corresponds to a grayscale intensity of the pixel to be printed. The arrangement includes at least a first delay line including an input, an output and a plurality of cells serially connected therebetween such that a digital signal received by the input propagates from the input to the output through the cells. Each cell includes a cell output for indication of the present state of digital data contained in the cell. A pulse generating section then provides the clock signal, as the digital signal, to the input of the first delay line such that the clock signal propagates through the first delay line. Thereafter, a processing section reads the cell output of a first one of the cells at a first position on the first delay line and then reads the cell output of a second one of the cells at a second, subsequent position on the first delay line to form the variable width pulse width having a width defined as the propagation time of the clock signal from the first position to the second position on the first delay line.

Claims

1. In an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on eight bits of digital data, an arrangement for producing a series of variable width pulses during clock intervals which are established by a clock signal such that the width of one variable width pulse produced during each clock interval is based on said digital data and corresponds to a grayscale intensity associated with said pixel, said arrangement comprising:

a) a first delay line arrangement and a second delay line arrangement including first and second delay lines, respectively, and each delay line including an input, an output and a plurality of 256 cells serially connected therebetween such that a digital signal received by the input of either delay line propagates from the input of the delay line to the output of the delay line through said cells, each cell including a cell output for indication of the present state of digital data contained in that cell;

b) input means for alternating the clock signal in one interval to the input of the first delay line and in the next interval to the input of the second delay line as said digital signal such that only one delay line arrangement is active at a time and the clock signal propagates through the first delay line during odd numbered clock intervals and through the second delay line in even numbered clock intervals; and

c) processing means including

i) control means configured for varying the locations of said first position and a second position along said first or second delay line such that the position and/or width of said pulse is variable within said clock interval,

ii) first means for reading the cell output of a first one of said cells at a first position on said first or second delay line and, thereafter, for reading the cell output of a second one of said cells at a second, subsequent position on said first or second delay line and, thereafter, for forming said variable width pulse width having a width defined as the propagation time of said clock signal from said first position to said second position on the active one of the first or second delay line, said first and a subsequent second means each including first and second multiplexers configured for reading the cells of said first or second delay line, respectively, and having first and second inputs for specifying the cells corresponding to said first and second positions in a predetermined way such that the first multiplexer establishes a start time for said variable width pulse by outputting a first output signal when said clock signal reaches said first position and the second multiplexer establishes a stop time for said variable width pulse by outputting a second output signal when said clock signal reaches said second position,

iii) a digital processing arrangement receiving said eight bits of digital data for use in specifying said first and second positions in said predetermined way by generating eight start bits for use by said first multiplexer of said first and second means specifying the cell at said first position and by generating eight stop bits for use by said second multiplexer of said first and second means specifying the cell at said second position, said digital processing arrangement further including first and second flip-flops each of which includes a flip-flop output and a flip flop input, said first flip-flop receiving said first output signal from said first multiplexer of said first means as one flip-flop clock signal and receiving said second output signal from said second multiplexer of said first means as one flip-flop reset signal and said second flip-flop receiving said first output signal from said first multiplexer of said second means as another flip-flop clock signal and receiving said second output signal from said second multiplexer of said second means as another flip-flop reset signal such that the first and second flip-flops alternately output one variable width pulse,

iv) means for combining the alternate output of said variable width pulse from the first and second flip-flops to form said series of variable width pulses;

d) a calibration arrangement including

i) a third delay line including an input, an output and a configuration having 256 cells for producing delays substantially identical to those produced by said first and second delay line under identical operating conditions on digital information received by the input of the third delay line and, thereafter, propagating to the output of the third delay line, said input of the third delay line receiving said clock signal as said digital information such that the output of said third delay line is a delayed clock signal, each cell of said first, second and third delay lines further including a delay control input which establishes delay time provided by each cell,

ii) discriminator means cooperating with said third delay line for comparing said delayed clock signal with said clock signal in a way which produces a difference signal, and

iii) converter means for receiving said difference signal and for producing a cell drive signal responsive to said difference signal which cell drive signal is coupled to the delay control input of each cell of the first, second and third delay lines in a way which reduces said difference signal such that the delay time of each cell of said first, second and third delay lines changes to more closely match the duration of one clock interval.

2. In an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on predetermined digital data, an arrangement for producing a variable width pulse during a clock interval which is established by a clock signal such that the width of said pulse during the clock interval is based on said digital data and corresponds to a grayscale intensity associated with said pixel, said arrangement comprising:

a) at least a first delay line including an input, an output and a plurality of cells serially connected therebetween such that a digital signal received by said input propagates from the input to the output through said cells, each cell including a cell output for indication of the present state of digital data contained in the cell;

b) input means for providing the clock signal as said digital signal to the input of said first delay line such that the clock signal propagates through the first delay line; and

c) processing means for reading the cell output of a first one of said cells at a first position on said first delay line and, thereafter, for reading the cell output of a second one of said cells at a second, subsequent position on said first delay line and, thereafter, for forming said variable width pulse width having a width defined as the propagation time of said clock signal from said first position to said second position on the first delay line.

3. The arrangement of claim 2 wherein said processing means is configured for varying the locations of said first and second positions along said first delay line such that the position and/or width of said pulse is variable within said clock interval.

4. The arrangement of claim 3 wherein said processing means includes first means at least for reading the output of the cell at said first position and second means at least for reading the output of the cell at said second position.

5. The arrangement of claim 4 wherein said processing means includes a digital processing arrangement for receiving said digital data and for determining said first and second positions based on said digital data.

6. The arrangement of claim 4 wherein said first and second means include first and second multiplexers having first and second inputs, respectively, for receiving first and second selection data which specifies the cells corresponding to said first and second positions such that the first multiplexer establishes a start time for said variable width pulse and the second multiplexer establishes a stop time for said variable width pulse.

7. The arrangement of claim 6 wherein said first multiplexer and said second multiplexer are configured for reading all of the cells of said delay line.

8. The arrangement of claim 6 wherein said processing means includes a digital processing arrangement for receiving said digital data and for determining said first and second selection data based on said digital data and for providing the first and second selection data to said first and second multiplexers.

9. The arrangement of claim 8 wherein said first delay line includes 256 cells and said digital data is provided as eight bits and wherein said digital processing arrangement provides said first selection data as eight start bits to said first multiplexer specifying the cell at said first position and provides said second selection data as eight stop bits to said second multiplexer specifying the cell at said second position.

10. The arrangement of claim 6 wherein said first multiplexer includes a first output and said second multiplexer includes a second output such that the first multiplexer provides a first output signal when said clock signal propagates to said first position and said second multiplexer provides a second output signal when said clock signal propagates to said second position.

11. The arrangement of claim 10 wherein said digital processing arrangement includes a flip-flop having a flip-flop output and flip-flop inputs for receiving said first output signal from said first multiplexer as a clock signal and receiving said second output signal from said second multiplexer as a reset signal such that said flip-flop output produces said variable width pulse.

12. The arrangement of claim 2 further comprising:

d) a calibration arrangement including

i) a second delay line including an input, an output and a configuration for producing delays substantially identical to those produced by said first delay line under identical operating conditions on a digital signal received by the input of the second delay line and, thereafter, propagating to the output of the second delay line, said input of the second delay line receiving said clock signal as said digital signal such that the output of said second delay line is a delayed clock signal, each cell of said first and second delay lines further including a delay control input which establishes delay time provided by each cell,

ii) discriminator means cooperating with said second delay line for comparing said delayed clock signal with said clock signal in a way which produces a difference signal, and

iii) converter means for receiving said difference signal and for producing a cell drive signal responsive to said difference signal which cell drive signal is coupled to the delay control input of each cell of the first and second delay lines in a way which reduces said difference signal such that the overall delay time of said first and second delay lines changes to more closely match the duration of one clock interval.

13. The arrangement of claim 12 wherein said discriminator means includes a divide by two counter which produces a one-half frequency clock signal and a flip-flop which receives said one-half frequency clock signal and said delayed clock signal to generate said difference signal.

14. The arrangement of claim 12 wherein said converter means includes an up/down counter which counts in response to said difference signal to produce a difference count and a digital to analog converter which receives said difference count and produces an analog current for use in generating said cell drive signal.

15. The arrangement of claim 14 wherein said converter means includes a current to voltage converter which receives said analog current and, thereafter, produces said cell drive signal as an analog voltage.

16. The arrangement of claim 12 wherein each cell of said delay lines includes a current starved stage having a first output and which defines said delay control input and wherein each cell further includes a high gain stage having a second output such that (i) the delay control input of the current starved stage receives the cell drive input to then provide said first output to the high gain stage and (ii) said second output of the high gain stage is the cell output of the cell.

17. The arrangement of claim 2 wherein each cell of said delay line includes a current starved stage having a first output and a high gain stage having a second output such that the current starved stage provides said first output to the high gain stage and said second output of the high gain stage is the cell output of the cell.

18. In an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on predetermined digital data, an arrangement for producing a variable width pulse during a clock interval which is established by a clock signal such that the width of said pulse during the clock interval is based on said digital data and corresponds to a grayscale intensity associated with said pixel, said arrangement comprising:

a) a first delay line arrangement and a second delay line arrangement including first and second delay lines, respectively, and each delay line including an input, an output and a plurality of cells serially connected therebetween such that a digital signal received by the input of either delay line propagates from the input of the delay line to the output of the delay line through said cells, each cell including a cell output for indication of the present state of digital data contained in that cell;

b) input means for alternating the clock signal in one interval to the input of the first delay line and in the next interval to the input of the second delay line as said digital signal such that only one delay line arrangement is active at a time and the clock signal propagates through the first delay line during odd numbered clock intervals and through the second delay line in even numbered clock intervals; and

c) processing means for reading the cell output of a first one of said cells at a first position on said first or second delay line and, thereafter, for reading the cell output of a second one of said cells at a second, subsequent position on said first or second delay line and, thereafter, for forming said variable width pulse width having a width defined as the propagation time of said clock signal from said first position to said second position on the active one of the first or second delay line.

19. The arrangement of claim 18 wherein said processing means is configured for varying the locations of said first and second positions along said first and second delay line such that the position and/or width of said pulse is variable within said clock interval.

20. The arrangement of claim 19 wherein said processing means includes first means for reading the output of the cell at said first position and said second position on said first delay line and second means for reading the output of the cell at said first position and said second position on said second delay line.

21. The arrangement of claim 20 wherein said processing means includes a digital processing arrangement for receiving said digital data and for determining said first and second positions based on said digital data.

22. The arrangement of claim 20 wherein said first and second means each include first and second multiplexers having first and second inputs, respectively, for receiving first and second selection data which specifies the cells corresponding to said first and second positions such that the first multiplexer establishes a start time for said variable width pulse and the second multiplexer establishes a stop time for said variable width pulse.

23. The arrangement of claim 22 wherein said first multiplexer and said second multiplexer associated with said first or second delay line are configured for reading all of the cells of said first and second delay line.

24. The arrangement of claim 22 wherein said processing means includes a digital processing arrangement for receiving said predetermined digital data and for determining said first and second selection data based on said predetermined digital data and then providing the first and second selection data to said first and second multiplexers associated with the first and second means.

25. The arrangement of claim 24 wherein said digital data is provided as eight bits and wherein said first second delay lines each include 256 cells and said digital processing arrangement provides said first selection data as eight start bits to said first multiplexer of said first and second means specifying the cell at said first position and provides said second selection data as eight stop bits to said second multiplexer of said first and second means specifying the cell at said second position.

26. The arrangement of claim 22 wherein said first multiplexer of said first and second means includes a first output and said second multiplexer of said first and second means includes a second output such that the first multiplexer provides a first output signal when said clock signal propagates to said first position and said second multiplexer provides a second output signal when said clock signal propagates to said second position.

27. The arrangement of claim 26 wherein said digital processing arrangement includes first and second flip-flops each of which includes a flip-flop output and a flip flop input, said first flip-flop receiving said first output signal from said first multiplexer of said first means as a clock signal and receiving said second output signal from said second multiplexer of said first means as a reset signal and said second flip-flop receiving said first output signal from said first multiplexer of said second means as a clock signal and receiving said second output signal from said second multiplexer of said second means as a reset signal such that the first and second flip-flops alternately output said variable width pulse.

28. The arrangement of claim 27 wherein said digital processing arrangement includes combining means for combining the alternate output of said variable width pulse from the first and second flip-flops.

29. In an electrostatic printing mechanism which is adapted to produce grayscale intensity of a pixel to be printed based on predetermined digital data having an pulse generating arrangement including at least a first delay line for producing a variable width pulse during a clock interval which is established by a clock signal such that the width of said pulse during the clock interval is based on said digital data and corresponds to a grayscale intensity associated with said pixel, said first delay line including at least one calibration drive input which varies delay produced thereby, a calibration arrangement acting in a way which stabilizes the output of said pulse generating arrangement, said calibration arrangement comprising:

a) a second delay line including an input, an output, a calibration drive input and a configuration for producing delays substantially identical to those produced by said first delay line under identical operating conditions on a digital signal received by the input of the second delay line and, thereafter, propagating to the output of the second delay line, said input of the second delay line receiving said clock signal as said digital signal such that the output of said second delay line is a delayed clock signal;

b) discriminator means cooperating with said second delay line for comparing said delayed clock signal with said clock signal in a way which produces a difference signal, and

c) converter means for receiving said difference signal and for producing a calibration drive signal responsive to said difference signal which calibration drive signal is coupled to the calibration drive inputs of said first and second delay lines in a way which reduces said difference signal such that the delay produced by said first and second delay lines changes to more closely match the duration of one clock interval.

30. The calibration arrangement of claim 29 wherein said discriminator means includes a divide by two counter which produces a one-half frequency clock signal and a flip-flop which receives said one-half frequency clock signal and said delayed clock signal to generate said difference signal.

31. The calibration arrangement of claim 29 wherein said converter means includes an up/down counter which counts in response to said difference signal to produce a difference count and a digital to analog converter which receives said difference count and produces an analog current for use in generating said calibration drive signal.

32. The calibration arrangement of claim 31 wherein said converter means includes a current to voltage converter which receives said analog current and, thereafter, produces said calibration drive signal as an analog voltage.