Reduced common voltage in a DC matrix converter

• US 6,166,930 A
• Filed: 05/12/1999
• Issued: 12/26/2000
• Est. Priority Date: 05/12/1999
• Status: Expired due to Term

• Current Assignee: Otis Elevator Company (Otis Worldwide Corp.), SubAir Incorporated
• Original Assignee: Otis Elevator Company (Otis Worldwide Corp.)
• Inventors: Czerwinski, Christopher S.
• Primary Examiner(s): Riley, Shawn
• Application Number:
  US09/310,311
• Time in Patent Office: 594 Days
• Field of Search: 363/39, 363/44, 318/811
• US Class Current: 363/44
• CPC Class Codes: H02M 5/271 from a three phase input voltage
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/53876 based on synthesising a desired voltage vector via the selection of appropriate fundamental voltage vectors, and corresponding dwelling times
• CPC Class Codes: H02P 29/50 Reduction of harmonics
• CPC Class Codes: H02P 7/2815 whereby the speed is regulated by measuring the motor speed and comparing it with a given physical value

Abstract

A DC matrix converter having six forward current conducting power switches and six reverse current conducting power switches has the on time duration of each power switch within each pulse width modulation period controlled by relationships between d, q components of a modulation index determined by the ratio of a voltage command to the instantaneous voltage of the AC mains expressed in stationary d, q coordinates, the selection of which is made based on inequalities between the AC mains voltage components expressed in dq coordinates, and relationships of the AC main voltage components expressed in d, q coordinates. Zero vectors are related to the one AC main having lower line-to-neutral voltage than the other AC mains, using relationships between the instantaneous AC mains voltage in d, q coordinates.

Claims

1. A method of controlling the flow of current through a DC matrix converter between a DC load and a set of three-phase AC mains, said DC matrix converter comprising a plurality of top switches, each connected between a corresponding one of said AC mains and a first DC output of said DC matrix converter, and a plurality of bottom switches, each connected between a corresponding one of said AC mains and a second DC output of said DC matrix converter, comprising:

operating said switches in a manner so that each switch, when operated to connect a corresponding one of said AC mains to a related specific one of said DC outputs, remains operated until another switch has operated to connect one of said AC mains to said specific DC output, and so that one of said top switches is operated contemporaneously with one of said bottom switches, said switches being operated in pairs, each pair including a top switch related to one AC main and a bottom switch related to an AC main other than said one AC main, and said switches also being operated in sets, each set including a top switch and a bottom switch both related to the same AC main;

in each of a continuous sequence of modulation periods which are small compared with the period of voltage of said AC mains, operating a first pair of said switches for a first fraction, dα

, of said period, operating a second pair of said switches for a second fraction, dβ

, of said period, and operating a set of switches for the remainder of said period; and

selecting said set of switches in any modulation period to be a set related to a selected AC main for which the line-to-neutral voltage of said selected AC main is less than the line-to-neutral voltage of the other two of said AC mains.

2. A method according to claim 1 further comprising:

selecting said selected AC main to be one whose instantaneous phase is within π

/6 of a zero crossing point of the voltage of said selected AC main.

3. A method according to claim 1 wherein

when the present instantaneous phase, ω

t, of said AC mains voltage in stationary d, q coordinates is π

/3<

ω

t<

2π

/3 or 4π

/3<

ω

t<

5π

/3, where ω

t is zero corresponding to the peak of the line voltage of a first one of said AC mains, said selected AC main is said first AC main;

when said instantaneous phase is 0<

ω

t<

π

/3 or π

<

ω

t<

4π

/3, said selected AC main is a second one of said AC mains next delayed in phase from said first AC main; and

when said instantaneous phase is 2π

/3<

ω

t<

π

/3 or 5π

/3<

ω

t<

0, said selected AC main is a third one of said AC mains next advanced in phase from said first AC main.

4. A method according to claim 3 further comprising:

providing an in-phase component, Vq, and a quadrature component, Vd, of the current instantaneous AC mains voltage in orthogonal d, q coordinates;

identifying said instantaneous phase to be π

/3<

ω

t<

2π

/3 or 4π

/3<

ω

t<

5π

/3 by a first relationship, |Vd|>

|Vq√

3|;

identifying said instantaneous phase to be 0<

ω

t<

π

/3 or π

<

ω

t<

4π

/3 by a second relationship, Vd² <

Vd Vq√

3; and

identifying said instantaneous phase to be 2π

/3<

ω

t<

π

/3 or 5π

/3<

ω

t<

0 by the absence of both said first relationship and said second relationship.

5. A method of controlling the flow of current through a DC matrix converter between a DC load and a set of three-phase AC mains, said DC matrix converter comprising a plurality of top switches, each connected between a corresponding one of said AC mains and a first DC output of said DC matrix converter, and a plurality of bottom switches, each connected between a corresponding one of said AC mains and a second DC output of said DC matrix converter, comprising:

operating said switches in a manner so that each switch, when operated to connect a corresponding one of said AC mains to a related specific one of said DC outputs, remains operated until another switch has operated to connect one of said AC mains to said specific DC output, and so that one of said top switches is operated contemporaneously with one of said bottom switches, said switches being operated in pairs, each pair including a top switch related to one AC main and a bottom switch related to an AC main other than said one AC main, and said switches also being operated in sets, each set including a top switch and a bottom switch both related to the same AC main;

providing an in phase component, Vq, and a quadrature component, Vd, of the current instantaneous AC mains voltage in orthogonal d, q coordinates;

in each of a continuous sequence of modulation periods which are small compared with the period of voltage of said AC mains, operating a first pair of said switches for a first fraction, dα

, of said period, operating a second pair of said switches for a second fraction, dβ

, of said period, and operating a set of switches for the remainder of said period;

if |Vd|>

|Vq√

3|, operating the one of said sets connected to a first one of said AC mains which is aligned with the Vq axis;

if Vd² <

VdVq√

3, operating the one of said sets connected to a second one of said AC mains next delayed in phase from said first AC main; and

if neither |Vd|>

|Vq√

3| nor Vd² <

VdVq√

3, operating the one of said sets connected to a third one of said AC mains next advanced in phase from said first AC main.